Cortex-R82: Start tasks at EL0

This commit includes the following changes

* Currently, the expectation is that applications
would explicitly call xPortStartScheduler() on all
secondary cores. However, this approach places an
unnecessary burden on the application developer and
assumes strict adherence to our example code,
which we cannot guarantee.
To make the port more inclusive and align with the principle
that the kernel should take care of system responsibilities,
we are shifting this logic into the port itself.
With this change, the application developer only needs to call
vTaskStartScheduler() on the primary core, does an SVC call once
the secondary cores are online, and the kernel will ensure
that all secondary cores are properly managed.

* Support tasks running in EL0 and only kernel running in EL1,
the changes are just having multiple SVCs for different purposes
(whenever a privileged instruction (e.g., MSR) is to be executed).

Signed-off-by: Ahmed Ismail <Ahmed.Ismail@arm.com>

Author: AhmedIsmail02

portable/GCC/ARM_CR82/README.md

@@ -17,3 +17,26 @@ The port is supported and tested on the following toolchains:
 - This port assumes the hardware or model is fully cache coherent.
 - The port does not perform cache maintenance for shared buffers.
 - If your hardware or model doesn't support full cache coherency, you must handle cache clean/invalidate operations, memory attributes, and any additional barriers in your BSP/application (especially around shared-memory regions).
+
+# SMP Multicore Bring-up
+
+For SMP systems using this port, the application only needs to start the scheduler on the primary core and issue an SVC from each secondary core once they are online. The kernel coordinates the rest and ensures all cores are properly managed.
+
+- Developer-facing summary: call `vTaskStartScheduler()` on the primary core; each secondary core, in its **reset handler**, performs its local init and then issues an SVC (immediate value `106`) to hand off to the kernel. The port will bring all cores under the scheduler.
+
+Primary core flow:
+
+1. Perform core-specific and shared initialization (e.g., set EL1 stack pointer, zero-initialize `.bss`).
+2. Jump to `main()`, create user tasks, optionally pin tasks to specific cores.
+3. Call `vTaskStartScheduler()` which invokes `xPortStartScheduler()`.
+4. `xPortStartScheduler()` configures the primary core tick timer and signals secondary cores that shared init is complete using the `ucPrimaryCoreInitDoneFlag` variable.
+5. Wait until all secondary cores report as brought up.
+6. Once all cores are up, call `vPortRestoreContext()` to schedule the first task on the primary core.
+
+Secondary core flow (to be done in each core’s reset handler):
+
+1. Perform core-specific initialization (e.g., set EL1 stack pointer).
+2. Wait for the primary core's signal that shared initialization is complete (i.e., `ucPrimaryCoreInitDoneFlag` set to 1).
+3. Update `VBAR_EL1` from the boot vector table to the FreeRTOS vector table.
+4. Initialize the GIC redistributor and enable SGIs so interrupts from the primary core are receivable; signal the primary that this secondary is online and ready by setting the its flag in the `ucSecondaryCoresReadyFlags` array.
+5. Issue an SVC with immediate value `106` to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on this core.

portable/GCC/ARM_CR82/port.c

@@ -88,27 +88,8 @@
  * this value. */
 #define portNO_CRITICAL_NESTING    ( ( size_t ) 0 )
 
-/* In all GICs 255 can be written to the priority mask register to unmask all
- * (but the lowest) interrupt priority. */
-#define portUNMASK_VALUE           ( 0xFFUL )
-
 /* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_PRIORITIES_MASK()          \
-    {                                                  \
-        __asm volatile (                               \
-            "MSR DAIFSET, #2        \n"                \
-            "DSB SY                 \n"                \
-            "ISB SY                 \n"                \
-            "MSR ICC_PMR_EL1, %0   \n"                 \
-            "DSB SY                 \n"                \
-            "ISB SY                 \n"                \
-            "MSR DAIFCLR, #2        \n"                \
-            "DSB SY                 \n"                \
-            "ISB SY                 \n"                \
-            :                                          \
-            : "r" ( portUNMASK_VALUE )                 \
-        );                                             \
-    }
+#define portCLEAR_INTERRUPT_PRIORITIES_MASK()    __asm volatile ( "SVC %0" : : "i" ( portSVC_UNMASK_ALL_INTERRUPTS ) : "memory" )
 
 /* Tasks are not created with a floating point context, but can be given a
  * floating point context after they have been created.  A variable is stored as
@@ -121,8 +102,9 @@
 #define portSP_ELx                       ( ( StackType_t ) 0x01 )
 #define portSP_EL0                       ( ( StackType_t ) 0x00 )
 #define portEL1                          ( ( StackType_t ) 0x04 )
+#define portEL0                          ( ( StackType_t ) 0x00 )
 
-#define portINITIAL_PSTATE               ( portEL1 | portSP_EL0 )
+#define portINITIAL_PSTATE               ( portEL0 | portSP_EL0 )
 
 /* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
  * point is zero. */
@@ -178,8 +160,9 @@ extern void vGIC_EnableCPUInterface( void );
     uint64_t ullPortYieldRequired[ configNUMBER_OF_CORES ] = { pdFALSE };
     uint64_t ullPortInterruptNestings[ configNUMBER_OF_CORES ] = { 0 };
 
-    /* Flag to control tick ISR handling, this is made true just before schedular start. */
-    uint8_t ucPortSchedulerRunning = pdFALSE;
+    /* Flags to check if the secondary cores are ready. */
+    volatile uint8_t ucSecondaryCoresReadyFlags[ configNUMBER_OF_CORES - 1 ] = { 0 };
+    volatile uint8_t ucPrimaryCoreInitDoneFlag = 0;
 #endif /* #if ( configNUMBER_OF_CORES == 1 ) */
 
 /* Used in the ASM code. */
@@ -320,39 +303,36 @@ BaseType_t xPortStartScheduler( void )
 
     #if ( configASSERT_DEFINED == 1 )
     {
-        if ( portGET_CORE_ID() == 0 )
-        {
-            volatile uint8_t ucOriginalPriority;
-            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
-            volatile uint8_t ucMaxPriorityValue;
+        volatile uint8_t ucOriginalPriority;
+        volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+        volatile uint8_t ucMaxPriorityValue;
 
-            /* Determine how many priority bits are implemented in the GIC.
-             *
-             * Save the interrupt priority value that is about to be clobbered. */
-            ucOriginalPriority = *pucFirstUserPriorityRegister;
+        /* Determine how many priority bits are implemented in the GIC.
+            *
+            * Save the interrupt priority value that is about to be clobbered. */
+        ucOriginalPriority = *pucFirstUserPriorityRegister;
 
-            /* Determine the number of priority bits available.  First write to
-             * all possible bits. */
-            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+        /* Determine the number of priority bits available.  First write to
+            * all possible bits. */
+        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 
-            /* Read the value back to see how many bits stuck. */
-            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+        /* Read the value back to see how many bits stuck. */
+        ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 
-            /* Shift to the least significant bits. */
-            while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
-            {
-                ucMaxPriorityValue >>= ( uint8_t ) 0x01;
-            }
+        /* Shift to the least significant bits. */
+        while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+        {
+            ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+        }
 
-            /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
-             * value. */
-            configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
+        /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+            * value. */
+        configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
 
 
-            /* Restore the clobbered interrupt priority register to its original
-             * value. */
-            *pucFirstUserPriorityRegister = ucOriginalPriority;
-        }
+        /* Restore the clobbered interrupt priority register to its original
+            * value. */
+        *pucFirstUserPriorityRegister = ucOriginalPriority;
     }
     #endif /* configASSERT_DEFINED */
 
@@ -365,20 +345,36 @@ BaseType_t xPortStartScheduler( void )
      * not execute while the scheduler is being started.  Interrupts are
      * automatically turned back on in the CPU when the first task starts
      * executing. */
-    portDISABLE_INTERRUPTS();
+    __asm volatile ( "MSR DAIFSET, #2\n"
+                     "DSB SY\n"
+                     "ISB SY\n" ::: "memory" );
     #if ( configNUMBER_OF_CORES > 1 )
-        if( portGET_CORE_ID() == 0 )
-        {
-            /* Start the timer that generates the tick ISR. */
-            configSETUP_TICK_INTERRUPT();
-            ucPortSchedulerRunning = pdTRUE;
-            __asm__ volatile ( "dsb sy" );
-            /* Start all other Cores and let them execute vPortRestoreTaskContext(). */
-             __asm__ volatile ( "sev" );
-        }
-        else
+        /* Start the timer that generates the tick ISR. */
+        configSETUP_TICK_INTERRUPT();
+        ucPrimaryCoreInitDoneFlag = 1;
+        __asm volatile ( "SEV                       \n"
+                         "DSB SY                    \n"
+                         "ISB SY                    \n"
+                         ::: "memory" );
+        /* Hold the primary core here until all the secondary cores are ready, this would be achieved only when
+         * all elements of ucSecondaryCoresReadyFlags are set.
+         */
+        while( 1 )
         {
-            portSETUP_SGI_INTERRUPT();
+            BaseType_t xAllCoresReady = pdTRUE;
+            for( uint32_t ulCoreID = 0; ulCoreID < ( configNUMBER_OF_CORES - 1 ); ulCoreID++ )
+            {
+                if( ucSecondaryCoresReadyFlags[ ulCoreID ] != pdTRUE )
+                {
+                    xAllCoresReady = pdFALSE;
+                    break;
+                }
+            }
+
+            if ( xAllCoresReady == pdTRUE )
+            {
+                break;
+            }
         }
     #else /* if ( configNUMBER_OF_CORES > 1 ) */
         /* Start the timer that generates the tick ISR. */
@@ -478,7 +474,9 @@ void FreeRTOS_Tick_Handler( void )
 
     /* Ok to enable interrupts after the interrupt source has been cleared. */
     configCLEAR_TICK_INTERRUPT();
-    portENABLE_INTERRUPTS();
+    __asm volatile ( "MSR DAIFCLR, #2\n"
+                     "DSB SY\n"
+                     "ISB SY\n" ::: "memory" );
 
     #if ( configNUMBER_OF_CORES > 1 )
         UBaseType_t x = portENTER_CRITICAL_FROM_ISR();
@@ -525,41 +523,78 @@ void FreeRTOS_Tick_Handler( void )
 
 void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
 {
-    if( uxNewMaskValue == pdFALSE )
+    if( uxNewMaskValue == portUNMASK_VALUE )
     {
+        /* Unmask all interrupt priorities. */
         portCLEAR_INTERRUPT_PRIORITIES_MASK();
     }
+    else
+    {
+        __asm volatile (
+            "SVC %0 \n"
+            :
+            : "i" ( portSVC_UNMASK_INTERRUPTS ), "r" ( uxNewMaskValue )
+            : "memory"
+        );
+    }
 }
 
+void vPortClearInterruptMaskFromISR( UBaseType_t uxNewMaskValue )
+{
+    __asm volatile (
+        "MSR DAIFSET, #2        \n"
+        "DSB SY                 \n"
+        "ISB SY                 \n"
+        "MSR ICC_PMR_EL1, %0    \n"
+        "DSB SY                 \n"
+        "ISB SY                 \n"
+        "MSR DAIFCLR, #2        \n"
+        "DSB SY                 \n"
+        "ISB SY                 \n"
+        :
+        : "r" ( uxNewMaskValue )
+    );
+}
 /*-----------------------------------------------------------*/
 
 UBaseType_t uxPortSetInterruptMask( void )
 {
-    uint32_t ulReturn;
-    uint64_t ullPMRValue;
+    UBaseType_t ullPMRValue;
+
+    /* Use SVC so this can be called safely from EL0 tasks. */
+    __asm volatile (
+        "svc %1        \n"
+        "mov %0, x0    \n"
+        : "=r" ( ullPMRValue )
+        : "i" ( portSVC_MASK_ALL_INTERRUPTS )
+        : "x0", "memory"
+    );
+
+    return ullPMRValue;
+}
+
+/* EL1/ISR variant to avoid SVC from interrupt context. */
+UBaseType_t uxPortSetInterruptMaskFromISR( void )
+{
+    UBaseType_t ullPMRValue;
 
-    /* Interrupt in the CPU must be turned off while the ICCPMR is being
-     * updated. */
-    portDISABLE_INTERRUPTS();
     __asm volatile ( "MRS %0, ICC_PMR_EL1" : "=r" ( ullPMRValue ) );
 
-    if( ullPMRValue == ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+    if( ullPMRValue != ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
     {
-        /* Interrupts were already masked. */
-        ulReturn = pdTRUE;
-    }
-    else
-    {
-        ulReturn = pdFALSE;
-        __asm volatile ( "MSR ICC_PMR_EL1, %0      \n"
-                         "DSB SY                    \n"
-                         "ISB SY                    \n"
+        __asm volatile ( "MSR DAIFSET, #2        \n"
+                         "DSB SY                 \n"
+                         "ISB SY                 \n"
+                         "MSR ICC_PMR_EL1, %0    \n"
+                         "DSB SY                 \n"
+                         "ISB SY                 \n"
+                         "MSR DAIFCLR, #2        \n"
+                         "DSB SY                 \n"
+                         "ISB SY                 \n"
                          ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
     }
 
-    portENABLE_INTERRUPTS();
-
-    return ulReturn;
+    return ullPMRValue;
 }
 
 /*-----------------------------------------------------------*/
@@ -645,8 +680,9 @@ UBaseType_t uxPortSetInterruptMask( void )
             "dmb sy\n"
             "mov w1, #0\n"
             "str w1, [%x0]\n"
-            "dsb sy\n"
             "sev\n"
+            "dsb sy\n"
+            "isb sy\n"
             :
             : "r" ( ulLock )
             : "memory", "w1"
@@ -732,7 +768,13 @@ UBaseType_t uxPortSetInterruptMask( void )
 
                 while( prvSpinTrylock( &ulGateWord[ eLockNum ] ) != 0 )
                 {
-                    __asm volatile ( "wfe" );
+                    /* Follow Arm's recommended way of sleeping
+                     * sevl is used to prime the wait loop,
+                     * the first wfe wakes immediately as sevl has set the flag
+                     * the second wfe sleeps the core. This way the core is ensured
+                     * to sleep.
+                     */
+                    __asm volatile ( "sevl; wfe; wfe" );
                 }
             }
 
@@ -771,16 +813,14 @@ UBaseType_t uxPortSetInterruptMask( void )
 
     BaseType_t xPortGetCoreID( void )
     {
-        register BaseType_t xCoreID;
-
+        BaseType_t xCoreID;
         __asm volatile (
-            "mrs  x0, MPIDR_EL1\n"
-            "and  %0, x0, #0xFF\n"
+            "svc %1             \n"
+            "mov %0, x0         \n"
             : "=r" ( xCoreID )
-            :
-            : "memory", "x0"
-            );
-
+            : "i" ( portSVC_GET_CORE_ID )
+            : "x0", "memory"
+        );
         return xCoreID;
     }
 
@@ -814,7 +854,9 @@ UBaseType_t uxPortSetInterruptMask( void )
                         ::"r" ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) : "memory" );
 
         /* Ok to enable interrupts after the interrupt source has been cleared. */
-        portENABLE_INTERRUPTS();
+        __asm volatile ( "MSR DAIFCLR, #2\n"
+                         "DSB SY\n"
+                         "ISB SY\n" ::: "memory" );
 
         #if ( configNUMBER_OF_CORES == 1 )
             ullPortYieldRequired = pdTRUE;