Sequential traversal of qsg in a read/write command

[0x161e-swei]

I am looking at the coding implementing backend_rw in https://github.com/MoatLab/FEMU/blob/master/hw/femu/backend/dram.c#L43.

I am wondering if the assumption of this while loop holds across all devices:

    while (sg_cur_index < qsg->nsg) {
        cur_addr = qsg->sg[sg_cur_index].base + sg_cur_byte;
        cur_len = qsg->sg[sg_cur_index].len - sg_cur_byte;
        if (dma_memory_rw(qsg->as, cur_addr, mb + mb_oft, cur_len, dir, MEMTXATTRS_UNSPECIFIED)) {
            femu_err("dma_memory_rw error\n");
        }

This while loop iterates through the qsg list sequentially and issues DMA requests for each entry in the qsg list.
For a PRP based command, the qsg data structure is constructed again sequentially from the PRP list.

Is the code assuming that all devices will issue DMA request sequentially following the PRP list? No out-of-order processing of the PRP list is possible?