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suoto edited this page Feb 28, 2021 · 6 revisions

DVB FPGA Wiki

Components documentation

DVB-S2 Tx

dvbs2_tx block diagram
DVB-S2 Tx block diagram

This is the top module for the DVB-S2 transmitter, which instantiates the subcomponents needed by the standard. Note that a frame's configuration parameters accompanies the data using AXI's TID/TUSER, meaning each input frame can have different parameters.

AXI LDPC Encoder

axi_ldpc_encoder_core_block_diagram
AXI LDPC Encoder block diagram

Data frame is fed to the frame data (s_tdata) and DVB parameters should be synchronized with it.

Values from the DVB tables (Annexes B and C from ETSI EN 302 307-1 V1.4.1), are expanded to per bit and fed to the s_ldpc interface. This interface need 2 values: the actual frame offsets (s_ldpc_offset) and when to process another frame bit (s_ldpc_next).

When s_ldpc_tlast is received, accumulation is considered completed and the final accumulation begins, in which point the component will not accept any data until the output frame is fully written.

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