From 43276e6d4a070f09d7bc8588a62ab297efae1b66 Mon Sep 17 00:00:00 2001 From: icymanred <71398492+icymanred@users.noreply.github.com> Date: Fri, 24 Oct 2025 16:39:53 +0100 Subject: [PATCH 1/8] add vld1 multiple single elements support --- arch/armv7/armv7_disasm/armv7.h | 20 ++++++++++++++------ arch/armv7/il.cpp | 26 +++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 7 deletions(-) diff --git a/arch/armv7/armv7_disasm/armv7.h b/arch/armv7/armv7_disasm/armv7.h index 14ff191a3c..8f71582057 100644 --- a/arch/armv7/armv7_disasm/armv7.h +++ b/arch/armv7/armv7_disasm/armv7.h @@ -910,15 +910,23 @@ typedef union _ieee754 { float fvalue; }ieee754; -typedef union _ieee754_double { +typedef union _ieee754_double +{ uint64_t value; - struct { - uint64_t fraction:52; - uint64_t exponent:11; - uint64_t sign:1; + struct + { + uint64_t fraction : 52; + uint64_t exponent : 11; + uint64_t sign : 1; }; double fvalue; -}ieee754_double; +} ieee754_double; + +struct DoubleWordRegisterList +{ + uint8_t size; + uint8_t start; +}; #ifndef __cplusplus typedef enum OperandClass OperandClass; diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index 0d79bcf65c..fbbef27f5d 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -123,7 +123,31 @@ static void ConditionExecute(LowLevelILFunction& il, Condition cond, ExprId true il.AddInstruction(trueCase); il.MarkLabel(falseCode); } - +static size_t GetDataTypeSize(DataType dt) +{ + switch (dt) + { + case DT_I8: + case DT_8: + return 8; + break; + case DT_F16: + case DT_I16: + case DT_16: + return 16; + break; + case DT_F32: + case DT_I32: + case DT_32: + return 32; + break; + case DT_F64: + case DT_I64: + case DT_64: + return 64; + break; + } +}; static ExprId GetShifted(LowLevelILFunction& il, Register reg, uint32_t ShiftAmount, Shift shift) { From c6b62edf81ecbd60a1527ebcf66fb00d28600033 Mon Sep 17 00:00:00 2001 From: icymanred <71398492+icymanred@users.noreply.github.com> Date: Fri, 24 Oct 2025 16:41:31 +0100 Subject: [PATCH 2/8] vld1 --- arch/armv7/il.cpp | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index fbbef27f5d..dc8330d0d8 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -5110,6 +5110,31 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI ) ); break; + case ARMV7_VLD1: + ConditionExecute(addrSize, instr.cond, instr, il, [&](size_t addrSize, Instruction& instr, LowLevelILFunction& il) { + switch (op1.cls) + { + case OperandClass::REG_LIST_DOUBLE: + DoubleWordRegisterList reglist = ReadRegisterList(op1); + uint32_t dregsize = get_register_size(REG_D0); + uint32_t regsize = get_register_size(op2.reg); + uint32_t dataSizeInBytes = GetDataTypeSize(instr.dataType) / 8; + for (unsigned int i = 0; i < reglist.size; i++) + { + uint32_t curOffset = i * dataSizeInBytes; + uint32_t curregind = REG_D0 + reglist.start + i; + + il.AddInstruction(il.SetRegister(dregsize, curregind, + il.Load(dataSizeInBytes, il.Add(regsize, ILREG(op2), il.Const(regsize, curOffset))))); + } + if (op2.flags.wb) + { + il.AddInstruction(il.SetRegister( + regsize, op2.reg, il.Add(regsize, ILREG(op2), il.Const(regsize, dataSizeInBytes * reglist.size)))); + } + } + }); + break; default: //printf("Instruction: %s\n", get_operation(instr.operation)); ConditionExecute(il, instr.cond, il.Unimplemented()); From 73cabe08712a56bdbb8d264a3d3fd1fbf09eb0ee Mon Sep 17 00:00:00 2001 From: icymanred <71398492+icymanred@users.noreply.github.com> Date: Fri, 24 Oct 2025 16:42:53 +0100 Subject: [PATCH 3/8] missing func --- arch/armv7/il.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index dc8330d0d8..61477b39a0 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -123,6 +123,7 @@ static void ConditionExecute(LowLevelILFunction& il, Condition cond, ExprId true il.AddInstruction(trueCase); il.MarkLabel(falseCode); } +// Returns an instructions datatype size in bits static size_t GetDataTypeSize(DataType dt) { switch (dt) @@ -183,6 +184,18 @@ static ExprId GetShifted(LowLevelILFunction& il, Register reg, uint32_t ShiftAmo return 0; } } +static DoubleWordRegisterList ReadRegisterList(InstructionOperand instr) { + uint32_t val = instr.reg; + DoubleWordRegisterList dwrl; + #ifdef _MSC_VER + dwrl.size = __popcnt(val); + DWORD pos = 0; + _BitScanForward(&pos, val); + dwrl.start = pos; + + #else + dwrl.size = __builtin_popcount(val); + dwrl.start = __builtin_ctz(val); static ExprId GetShiftedOffset(LowLevelILFunction& il, InstructionOperand& op) From deb7f893ef1c1ffa0864130714f5672640e1dc5c Mon Sep 17 00:00:00 2001 From: icymanred <71398492+icymanred@users.noreply.github.com> Date: Fri, 24 Oct 2025 16:47:56 +0100 Subject: [PATCH 4/8] end macro --- arch/armv7/il.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index 61477b39a0..e6685753ee 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -197,6 +197,9 @@ static DoubleWordRegisterList ReadRegisterList(InstructionOperand instr) { dwrl.size = __builtin_popcount(val); dwrl.start = __builtin_ctz(val); + #endif + return dwrl; +} static ExprId GetShiftedOffset(LowLevelILFunction& il, InstructionOperand& op) { From 21a41def5b091a7f33e0cb9662d7e0ca4202b622 Mon Sep 17 00:00:00 2001 From: Peter LaFosse Date: Tue, 28 Oct 2025 08:53:31 -0400 Subject: [PATCH 5/8] Remove unnecessary break after return statement in arch/armv7/il.cpp Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- arch/armv7/il.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index e6685753ee..36dc2dc80c 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -131,22 +131,18 @@ static size_t GetDataTypeSize(DataType dt) case DT_I8: case DT_8: return 8; - break; case DT_F16: case DT_I16: case DT_16: return 16; - break; case DT_F32: case DT_I32: case DT_32: return 32; - break; case DT_F64: case DT_I64: case DT_64: return 64; - break; } }; From b1d3e22df8814687dfeceaeb937f51d3c6ef1397 Mon Sep 17 00:00:00 2001 From: Peter LaFosse Date: Tue, 28 Oct 2025 08:53:57 -0400 Subject: [PATCH 6/8] Remove trailing semicolon arch/armv7/il.cpp Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- arch/armv7/il.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index 36dc2dc80c..85bc4bf1d7 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -144,7 +144,7 @@ static size_t GetDataTypeSize(DataType dt) case DT_64: return 64; } -}; +} static ExprId GetShifted(LowLevelILFunction& il, Register reg, uint32_t ShiftAmount, Shift shift) { From ab1b511540c9751f30133bc7377135413f0320f7 Mon Sep 17 00:00:00 2001 From: Peter LaFosse Date: Tue, 28 Oct 2025 09:06:37 -0400 Subject: [PATCH 7/8] make ReadRegisterList accept a const reference arch/armv7/il.cpp Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com> --- arch/armv7/il.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index 85bc4bf1d7..881055c6b2 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -180,7 +180,7 @@ static ExprId GetShifted(LowLevelILFunction& il, Register reg, uint32_t ShiftAmo return 0; } } -static DoubleWordRegisterList ReadRegisterList(InstructionOperand instr) { +static DoubleWordRegisterList ReadRegisterList(const InstructionOperand& instr) { uint32_t val = instr.reg; DoubleWordRegisterList dwrl; #ifdef _MSC_VER From e7e53c8b8bd729347b2edbdd2c518696542af857 Mon Sep 17 00:00:00 2001 From: icymanred <71398492+icymanred@users.noreply.github.com> Date: Sat, 1 Nov 2025 20:01:11 +0000 Subject: [PATCH 8/8] add all data types for GetDataTypeSize function and default case, add default case for armv7 vld1 unimplemented operand that adds unimplemented instruction --- arch/armv7/il.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/armv7/il.cpp b/arch/armv7/il.cpp index 881055c6b2..9a5a5d2e07 100644 --- a/arch/armv7/il.cpp +++ b/arch/armv7/il.cpp @@ -128,21 +128,34 @@ static size_t GetDataTypeSize(DataType dt) { switch (dt) { + case DT_P8: + case DT_U8: case DT_I8: case DT_8: return 8; + case DT_P16: + case DT_U16: + case DT_S16: case DT_F16: case DT_I16: case DT_16: return 16; + case DT_P32: + case DT_U32: + case DT_S32 case DT_F32: case DT_I32: case DT_32: return 32; + case DT_P64: + case DT_U64: + case DT_S64: case DT_F64: case DT_I64: case DT_64: return 64; + default: + return 0; } } @@ -5144,6 +5157,9 @@ bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelI il.AddInstruction(il.SetRegister( regsize, op2.reg, il.Add(regsize, ILREG(op2), il.Const(regsize, dataSizeInBytes * reglist.size)))); } + default: + il.AddInstruction(il.Unimplemented()); + break; } }); break;