From 73984ff0c76e785b6a680d2966343045424f0767 Mon Sep 17 00:00:00 2001 From: Philipp Honysz Date: Wed, 7 May 2025 06:25:07 -0600 Subject: [PATCH 1/2] Fix various compile warnings --- lld/ELF/Arch/AIE.cpp | 5 +-- llvm/lib/Target/AIE/AIEInstrInfo.cpp | 39 +++++++++---------- .../lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp | 5 +-- .../MCTargetDesc/aie2p/AIE2PAsmBackend.cpp | 5 --- llvm/utils/TableGen/CodeGenFormat.cpp | 20 +++++++--- 5 files changed, 35 insertions(+), 39 deletions(-) diff --git a/lld/ELF/Arch/AIE.cpp b/lld/ELF/Arch/AIE.cpp index 6dc1e24aea38..db9887741e02 100644 --- a/lld/ELF/Arch/AIE.cpp +++ b/lld/ELF/Arch/AIE.cpp @@ -71,10 +71,7 @@ uint32_t AIE::calcEFlags() const { RelExpr AIE::getRelExpr(const RelType Type, const Symbol &S, const uint8_t *Loc) const { - switch (Type) { - default: - return R_ABS; - } + return R_ABS; } // Read an N byte value from Loc in little-endian fashion. diff --git a/llvm/lib/Target/AIE/AIEInstrInfo.cpp b/llvm/lib/Target/AIE/AIEInstrInfo.cpp index 0df2a3dc7ae3..6a123da1d9b0 100644 --- a/llvm/lib/Target/AIE/AIEInstrInfo.cpp +++ b/llvm/lib/Target/AIE/AIEInstrInfo.cpp @@ -271,7 +271,8 @@ unsigned getVCMPforPseudoVCMP(unsigned opcode) { case AIE::VCMP512_S8: return AIE::VCMP_S8; } - assert(false && "Illegal opcode"); + + llvm_unreachable("Illegal opcode"); } SmallVector @@ -656,25 +657,23 @@ std::optional AIEInstrInfo::getCombinedPostIncOpcode( unsigned AIEInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { unsigned Opcode = MI.getOpcode(); - switch (Opcode) { - default: { return get(Opcode).getSize(); } - // case TargetOpcode::EH_LABEL: - // case TargetOpcode::IMPLICIT_DEF: - // case TargetOpcode::KILL: - // case TargetOpcode::DBG_VALUE: - // return 0; - // case AIE::PseudoCALL: - // case AIE::PseudoTAIL: - // case AIE::PseudoLLA: - // return 8; - // case TargetOpcode::INLINEASM: - // case TargetOpcode::INLINEASM_BR: { - // const MachineFunction &MF = *MI.getParent()->getParent(); - // const auto &TM = static_cast(MF.getTarget()); - // return getInlineAsmLength(MI.getOperand(0).getSymbolName(), - // *TM.getMCAsmInfo()); - // } - } + return get(Opcode).getSize(); + // case TargetOpcode::EH_LABEL: + // case TargetOpcode::IMPLICIT_DEF: + // case TargetOpcode::KILL: + // case TargetOpcode::DBG_VALUE: + // return 0; + // case AIE::PseudoCALL: + // case AIE::PseudoTAIL: + // case AIE::PseudoLLA: + // return 8; + // case TargetOpcode::INLINEASM: + // case TargetOpcode::INLINEASM_BR: { + // const MachineFunction &MF = *MI.getParent()->getParent(); + // const auto &TM = static_cast(MF.getTarget()); + // return getInlineAsmLength(MI.getOperand(0).getSymbolName(), + // *TM.getMCAsmInfo()); + // } } std::pair diff --git a/llvm/lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp b/llvm/lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp index cf6b902c6af4..a35a9b9fb93a 100644 --- a/llvm/lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp +++ b/llvm/lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp @@ -109,8 +109,5 @@ bool AIEMCExpr::evaluateAsConstant(int64_t &Res) const { } int64_t AIEMCExpr::evaluateAsInt64(int64_t Value) const { - switch (Kind) { - default: - llvm_unreachable("Invalid kind"); - } + llvm_unreachable("Invalid kind"); } diff --git a/llvm/lib/Target/AIE/MCTargetDesc/aie2p/AIE2PAsmBackend.cpp b/llvm/lib/Target/AIE/MCTargetDesc/aie2p/AIE2PAsmBackend.cpp index f1dd10712287..b62d3a69c9f6 100644 --- a/llvm/lib/Target/AIE/MCTargetDesc/aie2p/AIE2PAsmBackend.cpp +++ b/llvm/lib/Target/AIE/MCTargetDesc/aie2p/AIE2PAsmBackend.cpp @@ -15,11 +15,6 @@ using namespace llvm; bool AIE2PAsmBackend::isCall(unsigned Opcode) const { - switch (Opcode) { - // TODO Add Call Opcode e.g. JL - default: - break; - } return false; } diff --git a/llvm/utils/TableGen/CodeGenFormat.cpp b/llvm/utils/TableGen/CodeGenFormat.cpp index 83c448a3191a..06f719ffd700 100644 --- a/llvm/utils/TableGen/CodeGenFormat.cpp +++ b/llvm/utils/TableGen/CodeGenFormat.cpp @@ -168,12 +168,20 @@ void CodeGenFormat::run(raw_ostream &o) { o << "const std::vector *" << Target.getName().str() << "MCFormats::getAlternateInstsOpcode"; o << "(unsigned int Opcode) const {\n"; - o << " switch (Opcode) {\n"; - o << " default:\n"; - o << " return nullptr;\n"; - for (unsigned int i = 0; i < PseudoInstFormats.size(); i++) - PseudoInstFormats[i].emitAlternateInstsOpcode(o, i); - o << " }\n}\n"; + + if (!PseudoInstFormats.empty()) { + + o << " switch (Opcode) {\n"; + o << " default:\n"; + o << " return nullptr;\n"; + for (unsigned int i = 0; i < PseudoInstFormats.size(); i++) + PseudoInstFormats[i].emitAlternateInstsOpcode(o, i); + o << " }\n}\n"; + + } else { + o << " return nullptr;\n"; + o << " }\n"; + } o << "#endif // GET_ALTERNATE_INST_OPCODE_FUNC\n\n"; if (InstFormats.size() > 0 && Slots.size() > 0) { From f6bf69e3c2d463dc08528e447fae0da2d645da42 Mon Sep 17 00:00:00 2001 From: Philipp Honysz Date: Wed, 7 May 2025 08:31:35 -0600 Subject: [PATCH 2/2] Format changes --- lld/ELF/Arch/AIE.cpp | 20 +- llvm/lib/Target/AIE/AIEInstrInfo.cpp | 244 +++++++++--------- .../lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp | 7 +- .../MCTargetDesc/aie2p/AIE2PAsmBackend.cpp | 4 +- llvm/utils/TableGen/CodeGenFormat.cpp | 13 +- 5 files changed, 143 insertions(+), 145 deletions(-) diff --git a/lld/ELF/Arch/AIE.cpp b/lld/ELF/Arch/AIE.cpp index db9887741e02..690d75e10382 100644 --- a/lld/ELF/Arch/AIE.cpp +++ b/lld/ELF/Arch/AIE.cpp @@ -40,7 +40,8 @@ class AIE final : public TargetInfo { uint32_t calcEFlags() const override; RelExpr getRelExpr(RelType Type, const Symbol &S, const uint8_t *Loc) const override; - void relocate(uint8_t *Loc, const Relocation &rel, uint64_t Val) const override; + void relocate(uint8_t *Loc, const Relocation &rel, + uint64_t Val) const override; private: void relocateAIE1(uint8_t *Loc, const Relocation &rel, uint64_t Val) const; @@ -70,7 +71,7 @@ uint32_t AIE::calcEFlags() const { } RelExpr AIE::getRelExpr(const RelType Type, const Symbol &S, - const uint8_t *Loc) const { + const uint8_t *Loc) const { return R_ABS; } @@ -281,14 +282,14 @@ static void patch16bytes(uint8_t *Loc, const uint64_t V, uint32_t Begin, void AIE::relocateAIE1(uint8_t *Loc, const Relocation &rel, uint64_t Val) const { if (errorHandler().verbose) - lld::outs() << "Relocation expr=" << rel.expr << " " << rel.type << "@" - << getErrorLocation(Loc) << "\n"; + lld::outs() << "Relocation expr=" << rel.expr << " " << rel.type << "@" + << getErrorLocation(Loc) << "\n"; // Relocation applied to debug_info if (rel.expr == R_NONE) { - checkUInt(Loc, Val, 20, rel); - patch4bytes(Loc, Val, 19, 0, 12); - return; + checkUInt(Loc, Val, 20, rel); + patch4bytes(Loc, Val, 19, 0, 12); + return; } switch (rel.type) { @@ -296,8 +297,9 @@ void AIE::relocateAIE1(uint8_t *Loc, const Relocation &rel, // automatically generated from the processor description. #include "AIE_rela.inc" - //72 : (symbol_addr_AR + addend ) : addr [19..0]@0 in w08[4] // with default addend 0 - //73 : (symbol_addr_AR + addend ) : addr [19..0]@0 in w32[1] // with default addend 0 + // 72 : (symbol_addr_AR + addend ) : addr [19..0]@0 in w08[4] // + // with default addend 0 73 : (symbol_addr_AR + addend ) : addr [19..0]@0 + // in w32[1] // with default addend 0 case 72: case 73: checkUInt(Loc, Val, 20, rel); diff --git a/llvm/lib/Target/AIE/AIEInstrInfo.cpp b/llvm/lib/Target/AIE/AIEInstrInfo.cpp index 6a123da1d9b0..170528befe72 100644 --- a/llvm/lib/Target/AIE/AIEInstrInfo.cpp +++ b/llvm/lib/Target/AIE/AIEInstrInfo.cpp @@ -48,9 +48,9 @@ AIEInstrInfo::AIEInstrInfo() FuncUnitWrapper::setFormatInterface(FormatInterface); } -ScheduleHazardRecognizer* -AIEInstrInfo::CreateTargetPostRAHazardRecognizer( - const InstrItineraryData *II, const ScheduleDAG *DAG) const { +ScheduleHazardRecognizer * +AIEInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, + const ScheduleDAG *DAG) const { // AIE has a fully exposed pipeline, so we have to insert // Noops in the case of instruction dependence hazards. @@ -116,29 +116,29 @@ void AIEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, (AIE::PTRRegClass.contains(SrcReg) && AIE::PTRRegClass.contains(DstReg))) { BuildMI(MBB, MBBI, DL, get(AIE::MOV), DstReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); } else if (AIE::SPRRegClass.contains(SrcReg) && AIE::GPRRegClass.contains(DstReg)) { BuildMI(MBB, MBBI, DL, get(AIE::MV_SPECIAL2R), DstReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); } else if (AIE::GPRRegClass.contains(SrcReg) && AIE::SPRRegClass.contains(DstReg)) { BuildMI(MBB, MBBI, DL, get(AIE::MV_R2SPECIAL), DstReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); } else if (AIE::SPRRegClass.contains(SrcReg) && AIE::PTRRegClass.contains(DstReg)) { Register GPRReg = AIE::r15; BuildMI(MBB, MBBI, DL, get(AIE::MV_SPECIAL2R), GPRReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); BuildMI(MBB, MBBI, DL, get(AIE::MOV), DstReg) - .addReg(GPRReg, getKillRegState(KillSrc)); + .addReg(GPRReg, getKillRegState(KillSrc)); } else if (AIE::PTRRegClass.contains(SrcReg) && AIE::SPRRegClass.contains(DstReg)) { Register GPRReg = AIE::r15; BuildMI(MBB, MBBI, DL, get(AIE::MOV), GPRReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); BuildMI(MBB, MBBI, DL, get(AIE::MV_R2SPECIAL), DstReg) - .addReg(GPRReg, getKillRegState(KillSrc)); + .addReg(GPRReg, getKillRegState(KillSrc)); } else if (AIE::SPRRegClass.contains(SrcReg) && AIE::SPRRegClass.contains(DstReg)) { Register GPRReg = AIE::r15; @@ -149,31 +149,31 @@ void AIEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } else if (AIE::VEC128RegClass.contains(SrcReg) && AIE::VEC128RegClass.contains(DstReg)) { BuildMI(MBB, MBBI, DL, get(AIE::MV_V), DstReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); } else if (AIE::VEC256RegClass.contains(SrcReg) && AIE::VEC256RegClass.contains(DstReg)) { BuildMI(MBB, MBBI, DL, get(AIE::MV_W), DstReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); } else if (AIE::VEC512RegClass.contains(SrcReg) && AIE::VEC512RegClass.contains(DstReg)) { BuildMI(MBB, MBBI, DL, get(AIE::MV_X), DstReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); } else if (AIE::VEC1024RegClass.contains(SrcReg) && AIE::VEC1024RegClass.contains(DstReg)) { // The 1024-bit registers share their high-order bits. - if(SrcReg == AIE::ya && DstReg == AIE::yd) { + if (SrcReg == AIE::ya && DstReg == AIE::yd) { BuildMI(MBB, MBBI, DL, get(AIE::MV_X), AIE::xd) - .addReg(AIE::xa, getKillRegState(KillSrc)); - } else if(SrcReg == AIE::yd && DstReg == AIE::ya) { + .addReg(AIE::xa, getKillRegState(KillSrc)); + } else if (SrcReg == AIE::yd && DstReg == AIE::ya) { BuildMI(MBB, MBBI, DL, get(AIE::MV_X), AIE::xa) - .addReg(AIE::xd, getKillRegState(KillSrc)); + .addReg(AIE::xd, getKillRegState(KillSrc)); } } else if (AIE::GPRRegClass.contains(SrcReg) && AIE::VEC256RegClass.contains(DstReg)) { // only for f32 type. BuildMI(MBB, MBBI, DL, get(AIE::S2V_SHIFTW0_R32), DstReg) - .addReg(DstReg, RegState::Undef) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(DstReg, RegState::Undef) + .addReg(SrcReg, getKillRegState(KillSrc)); } else if (AIE::mMv0Cg20RegClass.contains(SrcReg) && AIE::VEC256RegClass.contains(DstReg)) { // only for f32 type. Bounce through GPR @@ -187,14 +187,16 @@ void AIEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, AIE::GPRRegClass.contains(DstReg)) { // only for f32 type. BuildMI(MBB, MBBI, DL, get(AIE::S2V_EXT_R32), DstReg) - .addReg(TRI.getSubReg(SrcReg, AIE::sub_128bit_lo), getKillRegState(true)) - .addImm(0); + .addReg(TRI.getSubReg(SrcReg, AIE::sub_128bit_lo), + getKillRegState(true)) + .addImm(0); } else if (AIE::VEC256RegClass.contains(SrcReg) && AIE::PTRRegClass.contains(DstReg)) { // only for f32 type. BuildMI(MBB, MBBI, DL, get(AIE::S2V_EXT_P32), DstReg) - .addReg(TRI.getSubReg(SrcReg, AIE::sub_128bit_lo), getKillRegState(true)) - .addImm(0); + .addReg(TRI.getSubReg(SrcReg, AIE::sub_128bit_lo), + getKillRegState(true)) + .addImm(0); } else if (AIE::VEC256RegClass.contains(SrcReg) && AIE::mMv0Cg20RegClass.contains(DstReg)) { // only for f32 type. Bounce through GPR @@ -208,13 +210,15 @@ void AIEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } else if (AIE::mCRegClass.contains(SrcReg) && AIE::mCRegClass.contains(DstReg)) { BuildMI(MBB, MBBI, DL, get(AIE::MOV), TRI.getSubReg(DstReg, AIE::sub_32_lo)) - .addReg(TRI.getSubReg(SrcReg, AIE::sub_32_lo), getKillRegState(KillSrc)); + .addReg(TRI.getSubReg(SrcReg, AIE::sub_32_lo), + getKillRegState(KillSrc)); BuildMI(MBB, MBBI, DL, get(AIE::MOV), TRI.getSubReg(DstReg, AIE::sub_32_hi)) - .addReg(TRI.getSubReg(SrcReg, AIE::sub_32_hi), getKillRegState(KillSrc)); + .addReg(TRI.getSubReg(SrcReg, AIE::sub_32_hi), + getKillRegState(KillSrc)); } else if (AIE::ACC384RegClass.contains(SrcReg) && AIE::ACC384RegClass.contains(DstReg)) { BuildMI(MBB, MBBI, DL, get(AIE::ACCUMULATOR_MOVE), DstReg) - .addReg(SrcReg, getKillRegState(KillSrc)); + .addReg(SrcReg, getKillRegState(KillSrc)); } else { assert(false && "unhandled case in copyPhysReg"); } @@ -223,53 +227,53 @@ void AIEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, // Sometimes the instruction set encodes smaller registers (256-bit or 512-bit) // using a 1024-bit yreg and an offset. void getYRegForNarrowReg(Register &yreg, int &offset, Register wreg) { - switch(wreg.id()) { - case AIE::wr0: - case AIE::xa: - yreg = AIE::ya; - offset = 0; - return; - case AIE::wr1: - yreg = AIE::ya; - offset = 8; - return; - case AIE::wr2: - case AIE::xb: - yreg = AIE::ya; - offset = 16; - return; - case AIE::wr3: - yreg = AIE::ya; - offset = 24; - return; - case AIE::wd0: - case AIE::xd: - yreg = AIE::yd; - offset = 0; - return; - case AIE::wd1: - yreg = AIE::yd; - offset = 8; - return; + switch (wreg.id()) { + case AIE::wr0: + case AIE::xa: + yreg = AIE::ya; + offset = 0; + return; + case AIE::wr1: + yreg = AIE::ya; + offset = 8; + return; + case AIE::wr2: + case AIE::xb: + yreg = AIE::ya; + offset = 16; + return; + case AIE::wr3: + yreg = AIE::ya; + offset = 24; + return; + case AIE::wd0: + case AIE::xd: + yreg = AIE::yd; + offset = 0; + return; + case AIE::wd1: + yreg = AIE::yd; + offset = 8; + return; } assert(false && "Illegal register"); } // Given a VCMP512 pseudo-op, return the VCMP op with the corresponding type. unsigned getVCMPforPseudoVCMP(unsigned opcode) { - switch(opcode) { - case AIE::VCMP512GPR_S16: - case AIE::VCMP512_S16: - return AIE::VCMP_S16; - case AIE::VCMP512GPR_S32: - case AIE::VCMP512_S32: - return AIE::VCMP_S32; - case AIE::VCMP512GPR_U8: - case AIE::VCMP512_U8: - return AIE::VCMP_U8; - case AIE::VCMP512GPR_S8: - case AIE::VCMP512_S8: - return AIE::VCMP_S8; + switch (opcode) { + case AIE::VCMP512GPR_S16: + case AIE::VCMP512_S16: + return AIE::VCMP_S16; + case AIE::VCMP512GPR_S32: + case AIE::VCMP512_S32: + return AIE::VCMP_S32; + case AIE::VCMP512GPR_U8: + case AIE::VCMP512_U8: + return AIE::VCMP_U8; + case AIE::VCMP512GPR_S8: + case AIE::VCMP512_S8: + return AIE::VCMP_S8; } llvm_unreachable("Illegal opcode"); @@ -321,16 +325,13 @@ bool AIEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { Register yreg; int offset; getYRegForNarrowReg(yreg, offset, wreg); - BuildMI(MBB, MI, DL, get(AIE::MOV_U20), AIE::r15) - .addImm(offset); + BuildMI(MBB, MI, DL, get(AIE::MOV_U20), AIE::r15).addImm(offset); auto b = BuildMI(MBB, MI, DL, get(AIE::VFPMAC)); // Swap the first two operands if necessary - if(MI.getOpcode() == AIE::VFPMAC256GPR) - b.add(MI.getOperand(1)) - .add(MI.getOperand(0)); + if (MI.getOpcode() == AIE::VFPMAC256GPR) + b.add(MI.getOperand(1)).add(MI.getOperand(0)); else // VFPMAC256... - b.add(MI.getOperand(0)) - .add(MI.getOperand(1)); + b.add(MI.getOperand(0)).add(MI.getOperand(1)); b.add(MI.getOperand(2)) .addReg(yreg) @@ -351,16 +352,13 @@ bool AIEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { Register yreg; int offset; getYRegForNarrowReg(yreg, offset, wreg); - BuildMI(MBB, MI, DL, get(AIE::MOV_U20), AIE::r15) - .addImm(offset); + BuildMI(MBB, MI, DL, get(AIE::MOV_U20), AIE::r15).addImm(offset); auto b = BuildMI(MBB, MI, DL, get(AIE::VFPMUL)); // Swap the first two operands if necessary - if(MI.getOpcode() == AIE::VFPMUL256GPR) - b.add(MI.getOperand(1)) - .add(MI.getOperand(0)); + if (MI.getOpcode() == AIE::VFPMUL256GPR) + b.add(MI.getOperand(1)).add(MI.getOperand(0)); else // VFPMUL256... - b.add(MI.getOperand(0)) - .add(MI.getOperand(1)); + b.add(MI.getOperand(0)).add(MI.getOperand(1)); b.addReg(yreg) .addReg(AIE::r15, RegState::Kill) @@ -389,33 +387,29 @@ bool AIEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { getYRegForNarrowReg(y1reg, offset1, x1reg); getYRegForNarrowReg(y2reg, offset2, x2reg); assert(y1reg == y2reg); - BuildMI(MBB, MI, DL, get(AIE::MOV_U20), AIE::r15) - .addImm(offset1); - BuildMI(MBB, MI, DL, get(AIE::MOV_U20), AIE::r5) - .addImm(offset2); + BuildMI(MBB, MI, DL, get(AIE::MOV_U20), AIE::r15).addImm(offset1); + BuildMI(MBB, MI, DL, get(AIE::MOV_U20), AIE::r5).addImm(offset2); auto b = BuildMI(MBB, MI, DL, get(getVCMPforPseudoVCMP(MI.getOpcode()))); // Swap the first two operands if necessary - switch(MI.getOpcode()) { - case AIE::VCMP512GPR_S16: - case AIE::VCMP512GPR_S32: - case AIE::VCMP512GPR_U8: - case AIE::VCMP512GPR_S8: - b.add(MI.getOperand(1)) - .add(MI.getOperand(0)); - break; - case AIE::VCMP512_S16: - case AIE::VCMP512_S32: - case AIE::VCMP512_U8: - case AIE::VCMP512_S8: - b.add(MI.getOperand(0)) - .add(MI.getOperand(1)); + switch (MI.getOpcode()) { + case AIE::VCMP512GPR_S16: + case AIE::VCMP512GPR_S32: + case AIE::VCMP512GPR_U8: + case AIE::VCMP512GPR_S8: + b.add(MI.getOperand(1)).add(MI.getOperand(0)); + break; + case AIE::VCMP512_S16: + case AIE::VCMP512_S32: + case AIE::VCMP512_U8: + case AIE::VCMP512_S8: + b.add(MI.getOperand(0)).add(MI.getOperand(1)); } b.addReg(y1reg) .addReg(AIE::r15, RegState::Kill) // xstart - .add(MI.getOperand(4)) // xoffs - .addReg(AIE::r5, RegState::Kill) // ystart - .add(MI.getOperand(5)) // yoffs - .add(MI.getOperand(6)); // conf + .add(MI.getOperand(4)) // xoffs + .addReg(AIE::r5, RegState::Kill) // ystart + .add(MI.getOperand(5)) // yoffs + .add(MI.getOperand(6)); // conf MI.eraseFromParent(); return true; @@ -598,7 +592,8 @@ void AIEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, I, DL, get(inst), DstReg).addReg(Reg, getKillRegState(true)); return; } else - llvm_unreachable("Can't load this register from stack slot: is it virtual?"); + llvm_unreachable( + "Can't load this register from stack slot: is it virtual?"); // To load from a stack slot we generate a load indirect via the // stack pointer. The actual offset will be an immediate, but for @@ -655,25 +650,25 @@ std::optional AIEInstrInfo::getCombinedPostIncOpcode( } unsigned AIEInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { - unsigned Opcode = MI.getOpcode(); - - return get(Opcode).getSize(); - // case TargetOpcode::EH_LABEL: - // case TargetOpcode::IMPLICIT_DEF: - // case TargetOpcode::KILL: - // case TargetOpcode::DBG_VALUE: - // return 0; - // case AIE::PseudoCALL: - // case AIE::PseudoTAIL: - // case AIE::PseudoLLA: - // return 8; - // case TargetOpcode::INLINEASM: - // case TargetOpcode::INLINEASM_BR: { - // const MachineFunction &MF = *MI.getParent()->getParent(); - // const auto &TM = static_cast(MF.getTarget()); - // return getInlineAsmLength(MI.getOperand(0).getSymbolName(), - // *TM.getMCAsmInfo()); - // } + unsigned Opcode = MI.getOpcode(); + + return get(Opcode).getSize(); + // case TargetOpcode::EH_LABEL: + // case TargetOpcode::IMPLICIT_DEF: + // case TargetOpcode::KILL: + // case TargetOpcode::DBG_VALUE: + // return 0; + // case AIE::PseudoCALL: + // case AIE::PseudoTAIL: + // case AIE::PseudoLLA: + // return 8; + // case TargetOpcode::INLINEASM: + // case TargetOpcode::INLINEASM_BR: { + // const MachineFunction &MF = *MI.getParent()->getParent(); + // const auto &TM = static_cast(MF.getTarget()); + // return getInlineAsmLength(MI.getOperand(0).getSymbolName(), + // *TM.getMCAsmInfo()); + // } } std::pair @@ -686,8 +681,7 @@ ArrayRef> AIEInstrInfo::getSerializableDirectMachineOperandTargetFlags() const { using namespace AIEII; static const std::pair TargetFlags[] = { - {MO_CALL, "aie-call"}, - {MO_GLOBAL, "aie-global"}}; + {MO_CALL, "aie-call"}, {MO_GLOBAL, "aie-global"}}; return ArrayRef(TargetFlags); } diff --git a/llvm/lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp b/llvm/lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp index a35a9b9fb93a..d7ea7b22698c 100644 --- a/llvm/lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp +++ b/llvm/lib/Target/AIE/MCTargetDesc/AIEMCExpr.cpp @@ -28,7 +28,7 @@ using namespace llvm; #define DEBUG_TYPE "aiemcexpr" const AIEMCExpr *AIEMCExpr::create(const MCExpr *Expr, VariantKind Kind, - MCContext &Ctx) { + MCContext &Ctx) { return new (Ctx) AIEMCExpr(Expr, Kind); } @@ -43,10 +43,9 @@ void AIEMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const { OS << ')'; } - bool AIEMCExpr::evaluateAsRelocatableImpl(MCValue &Res, - const MCAsmLayout *Layout, - const MCFixup *Fixup) const { + const MCAsmLayout *Layout, + const MCFixup *Fixup) const { // if (Kind == VK_AIE_PCREL_LO && evaluatePCRelLo(Res, Layout, Fixup)) // return true; diff --git a/llvm/lib/Target/AIE/MCTargetDesc/aie2p/AIE2PAsmBackend.cpp b/llvm/lib/Target/AIE/MCTargetDesc/aie2p/AIE2PAsmBackend.cpp index b62d3a69c9f6..52b625c1bb0e 100644 --- a/llvm/lib/Target/AIE/MCTargetDesc/aie2p/AIE2PAsmBackend.cpp +++ b/llvm/lib/Target/AIE/MCTargetDesc/aie2p/AIE2PAsmBackend.cpp @@ -14,9 +14,7 @@ using namespace llvm; -bool AIE2PAsmBackend::isCall(unsigned Opcode) const { - return false; -} +bool AIE2PAsmBackend::isCall(unsigned Opcode) const { return false; } bool AIE2PAsmBackend::isDelaySlotInstr(unsigned Opcode) const { switch (Opcode) { diff --git a/llvm/utils/TableGen/CodeGenFormat.cpp b/llvm/utils/TableGen/CodeGenFormat.cpp index 06f719ffd700..fa4cda04913f 100644 --- a/llvm/utils/TableGen/CodeGenFormat.cpp +++ b/llvm/utils/TableGen/CodeGenFormat.cpp @@ -689,7 +689,8 @@ void TGInstrLayout::emitFormat(ConstTable &FieldsHierarchy, ConstTable &o, << " " << (IsComposite ? "true" : "false") << " /* isComposite */,\n" << " " << (IsMultipleSlotOptions ? "true" : "false") << " /* hasMultipleSlotOptions */,\n" - << " " << "/* Slots - Fields mapper */\n" + << " " + << "/* Slots - Fields mapper */\n" << " {"; const std::string TargetClassName = Target + SlotsRegistry.GenSlotKindName; @@ -1105,7 +1106,8 @@ void TGTargetSlots::emitTargetSlotKindClass(raw_ostream &o) const { if (Slots.size() > 1) { // 2nd Ctor - Initilization by SlotKind if valid // We check in this constructor - o << " constexpr " << TargetEnumName << '(' << "int" << " Kind)\n" + o << " constexpr " << TargetEnumName << '(' << "int" + << " Kind)\n" << " : MC" << GenSlotKindName << "((Kind >= " // Default slot is always at index 0 @@ -1183,8 +1185,11 @@ void TGTargetSlots::emitTargetSlotClass(raw_ostream &o) const { << " const " << TargetEnumName << " Kind;\n" << "public:\n" << " constexpr " << TargetClassName << "(const " << TargetEnumName - << " Kind, " << "const char* SlotName, " << "unsigned Size, " - << "SlotBits SlotSet, " << "unsigned NopOpc)\n" + << " Kind, " + << "const char* SlotName, " + << "unsigned Size, " + << "SlotBits SlotSet, " + << "unsigned NopOpc)\n" << " : MC" << GenSlotInfoName << "(SlotName, Size, SlotSet, NopOpc), Kind(Kind)\n" << " {\n }\n\n"