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Add broadcast support for python binding packetflow op (#2573)
Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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+48
-57
lines changed

5 files changed

+48
-57
lines changed

‎programming_examples/basic/packet_switch/aie_add_placed.py‎

Lines changed: 7 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -111,65 +111,51 @@ def device_body():
111111
source=ShimTile_0_0,
112112
source_port=WireBundle.DMA,
113113
source_channel=0,
114-
dest=MemTile_0_1,
115-
dest_port=WireBundle.DMA,
116-
dest_channel=0,
114+
dests={"dest": MemTile_0_1, "port": WireBundle.DMA, "channel": 0},
117115
keep_pkt_header=True,
118116
)
119117
packetflow(
120118
pkt_id=1,
121119
source=ShimTile_0_0,
122120
source_port=WireBundle.DMA,
123121
source_channel=0,
124-
dest=MemTile_0_1,
125-
dest_port=WireBundle.DMA,
126-
dest_channel=0,
122+
dests={"dest": MemTile_0_1, "port": WireBundle.DMA, "channel": 0},
127123
keep_pkt_header=True,
128124
)
129125
packetflow(
130126
pkt_id=2,
131127
source=MemTile_0_1,
132128
source_port=WireBundle.DMA,
133129
source_channel=2,
134-
dest=ShimTile_0_0,
135-
dest_port=WireBundle.DMA,
136-
dest_channel=0,
130+
dests={"dest": ShimTile_0_0, "port": WireBundle.DMA, "channel": 0},
137131
)
138132
packetflow(
139133
pkt_id=0,
140134
source=MemTile_0_1,
141135
source_port=WireBundle.DMA,
142136
source_channel=0,
143-
dest=CT_0_2,
144-
dest_port=WireBundle.DMA,
145-
dest_channel=0,
137+
dests={"dest": CT_0_2, "port": WireBundle.DMA, "channel": 0},
146138
)
147139
packetflow(
148140
pkt_id=4,
149141
source=CT_0_2,
150142
source_port=WireBundle.DMA,
151143
source_channel=0,
152-
dest=MemTile_0_1,
153-
dest_port=WireBundle.DMA,
154-
dest_channel=2,
144+
dests={"dest": MemTile_0_1, "port": WireBundle.DMA, "channel": 2},
155145
)
156146
packetflow(
157147
pkt_id=1,
158148
source=MemTile_0_1,
159149
source_port=WireBundle.DMA,
160150
source_channel=0,
161-
dest=CT_0_3,
162-
dest_port=WireBundle.DMA,
163-
dest_channel=0,
151+
dests={"dest": CT_0_3, "port": WireBundle.DMA, "channel": 0},
164152
)
165153
packetflow(
166154
pkt_id=6,
167155
source=CT_0_3,
168156
source_port=WireBundle.DMA,
169157
source_channel=0,
170-
dest=MemTile_0_1,
171-
dest_port=WireBundle.DMA,
172-
dest_channel=2,
158+
dests={"dest": MemTile_0_1, "port": WireBundle.DMA, "channel": 2},
173159
)
174160

175161
# core_0_2 compute

‎programming_examples/basic/packet_switch/aie_mul_placed.py‎

Lines changed: 7 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -111,65 +111,51 @@ def device_body():
111111
source=ShimTile_0_0,
112112
source_port=WireBundle.DMA,
113113
source_channel=0,
114-
dest=MemTile_0_1,
115-
dest_port=WireBundle.DMA,
116-
dest_channel=0,
114+
dests={"dest": MemTile_0_1, "port": WireBundle.DMA, "channel": 0},
117115
keep_pkt_header=True,
118116
)
119117
packetflow(
120118
pkt_id=1,
121119
source=ShimTile_0_0,
122120
source_port=WireBundle.DMA,
123121
source_channel=0,
124-
dest=MemTile_0_1,
125-
dest_port=WireBundle.DMA,
126-
dest_channel=0,
122+
dests={"dest": MemTile_0_1, "port": WireBundle.DMA, "channel": 0},
127123
keep_pkt_header=True,
128124
)
129125
packetflow(
130126
pkt_id=2,
131127
source=MemTile_0_1,
132128
source_port=WireBundle.DMA,
133129
source_channel=2,
134-
dest=ShimTile_0_0,
135-
dest_port=WireBundle.DMA,
136-
dest_channel=0,
130+
dests={"dest": ShimTile_0_0, "port": WireBundle.DMA, "channel": 0},
137131
)
138132
packetflow(
139133
pkt_id=0,
140134
source=MemTile_0_1,
141135
source_port=WireBundle.DMA,
142136
source_channel=0,
143-
dest=CT_0_2,
144-
dest_port=WireBundle.DMA,
145-
dest_channel=0,
137+
dests={"dest": CT_0_2, "port": WireBundle.DMA, "channel": 0},
146138
)
147139
packetflow(
148140
pkt_id=4,
149141
source=CT_0_2,
150142
source_port=WireBundle.DMA,
151143
source_channel=0,
152-
dest=MemTile_0_1,
153-
dest_port=WireBundle.DMA,
154-
dest_channel=2,
144+
dests={"dest": MemTile_0_1, "port": WireBundle.DMA, "channel": 2},
155145
)
156146
packetflow(
157147
pkt_id=1,
158148
source=MemTile_0_1,
159149
source_port=WireBundle.DMA,
160150
source_channel=0,
161-
dest=CT_0_3,
162-
dest_port=WireBundle.DMA,
163-
dest_channel=0,
151+
dests={"dest": CT_0_3, "port": WireBundle.DMA, "channel": 0},
164152
)
165153
packetflow(
166154
pkt_id=6,
167155
source=CT_0_3,
168156
source_port=WireBundle.DMA,
169157
source_channel=0,
170-
dest=MemTile_0_1,
171-
dest_port=WireBundle.DMA,
172-
dest_channel=2,
158+
dests={"dest": MemTile_0_1, "port": WireBundle.DMA, "channel": 2},
173159
)
174160

175161
# core_0_2 compute

‎python/dialects/aie.py‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -509,17 +509,17 @@ def __init__(
509509
source,
510510
source_port,
511511
source_channel,
512-
dest,
513-
dest_port,
514-
dest_channel,
512+
dests: Union[Dict, List[Dict]],
515513
keep_pkt_header: bool | None = None,
516514
):
517515
super().__init__(ID=pkt_id, keep_pkt_header=keep_pkt_header)
518516
bb = Block.create_at_start(self.ports)
519517
with InsertionPoint(bb):
520-
src = PacketSourceOp(source, source_port, source_channel)
521-
dest = PacketDestOp(dest, dest_port, dest_channel)
522-
end = EndOp()
518+
PacketSourceOp(source, source_port, source_channel)
519+
dests = [dests] if isinstance(dests, dict) else dests
520+
for dest in dests:
521+
PacketDestOp(dest["dest"], dest["port"], dest["channel"])
522+
EndOp()
523523

524524

525525
core = region_op(Core, terminator=lambda *_: EndOp())

‎python/utils/trace.py‎

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1126,9 +1126,7 @@ def configure_packet_tracing_flow(tiles_to_trace, shim):
11261126
tiles_to_trace[i],
11271127
WireBundle.Trace,
11281128
0,
1129-
shim,
1130-
WireBundle.DMA,
1131-
1,
1129+
dests={"dest": shim, "port": WireBundle.DMA, "channel": 1},
11321130
keep_pkt_header=True,
11331131
)
11341132

@@ -1140,9 +1138,7 @@ def configure_packet_tracing_flow(tiles_to_trace, shim):
11401138
tiles_to_trace[i],
11411139
WireBundle.Trace,
11421140
1,
1143-
shim,
1144-
WireBundle.DMA,
1145-
1,
1141+
dests={"dest": shim, "port": WireBundle.DMA, "channel": 1},
11461142
keep_pkt_header=True,
11471143
)
11481144

‎test/python/aie_ops.py‎

Lines changed: 26 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -260,9 +260,32 @@ def packetFlowOp():
260260
source=t0,
261261
source_port=WireBundle.Core,
262262
source_channel=0,
263-
dest=t0,
264-
dest_port=WireBundle.Core,
265-
dest_channel=0,
263+
dests={"dest": t0, "port": WireBundle.Core, "channel": 0},
264+
keep_pkt_header=True,
265+
)
266+
267+
268+
# CHECK-LABEL: packetMultiFlowOp
269+
# CHECK: %[[VAL_0:.*]] = aie.tile(1, 3)
270+
# CHECK: %[[VAL_1:.*]] = aie.tile(2, 4)
271+
# CHECK: aie.packet_flow(16) {
272+
# CHECK: aie.packet_source<%[[VAL_0]], DMA : 0>
273+
# CHECK: aie.packet_dest<%[[VAL_0]], DMA : 1>
274+
# CHECK: aie.packet_dest<%[[VAL_1]], DMA : 1>
275+
# CHECK: } {keep_pkt_header = true}
276+
@construct_and_print_module
277+
def packetMultiFlowOp():
278+
t0 = tile(col=1, row=3)
279+
t1 = tile(col=2, row=4)
280+
packetflow(
281+
pkt_id=0x10,
282+
source=t0,
283+
source_port=WireBundle.DMA,
284+
source_channel=0,
285+
dests=[
286+
{"dest": t0, "port": WireBundle.DMA, "channel": 1},
287+
{"dest": t1, "port": WireBundle.DMA, "channel": 1},
288+
],
266289
keep_pkt_header=True,
267290
)
268291

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