fixup

Author: fifield

programming_examples/basic/packet_switch/aie_mul_placed.py

@@ -111,51 +111,51 @@ def device_body():
             source=ShimTile_0_0,
             source_port=WireBundle.DMA,
             source_channel=0,
-            dest=(MemTile_0_1, WireBundle.DMA, 0),
+            dests=(MemTile_0_1, WireBundle.DMA, 0),
             keep_pkt_header=True,
         )
         packetflow(
             pkt_id=1,
             source=ShimTile_0_0,
             source_port=WireBundle.DMA,
             source_channel=0,
-            dest=(MemTile_0_1, WireBundle.DMA, 0),
+            dests=(MemTile_0_1, WireBundle.DMA, 0),
             keep_pkt_header=True,
         )
         packetflow(
             pkt_id=2,
             source=MemTile_0_1,
             source_port=WireBundle.DMA,
             source_channel=2,
-            dest=(ShimTile_0_0, WireBundle.DMA, 0),
+            dests=(ShimTile_0_0, WireBundle.DMA, 0),
         )
         packetflow(
             pkt_id=0,
             source=MemTile_0_1,
             source_port=WireBundle.DMA,
             source_channel=0,
-            dest=(CT_0_2, WireBundle.DMA, 0),
+            dests=(CT_0_2, WireBundle.DMA, 0),
         )
         packetflow(
             pkt_id=4,
             source=CT_0_2,
             source_port=WireBundle.DMA,
             source_channel=0,
-            dest=(MemTile_0_1, WireBundle.DMA, 2),
+            dests=(MemTile_0_1, WireBundle.DMA, 2),
         )
         packetflow(
             pkt_id=1,
             source=MemTile_0_1,
             source_port=WireBundle.DMA,
             source_channel=0,
-            dest=(CT_0_3, WireBundle.DMA, 0),
+            dests=(CT_0_3, WireBundle.DMA, 0),
         )
         packetflow(
             pkt_id=6,
             source=CT_0_3,
             source_port=WireBundle.DMA,
             source_channel=0,
-            dest=(MemTile_0_1, WireBundle.DMA, 2),
+            dests=(MemTile_0_1, WireBundle.DMA, 2),
         )
 
         # core_0_2 compute