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tests: fix warnings about unclosed VCD files.
1 parent 6d83724 commit 45ff663

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8 files changed

+25
-25
lines changed

8 files changed

+25
-25
lines changed

‎tests/test_csr_action.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ def process():
2626

2727
sim = Simulator(dut)
2828
sim.add_testbench(process)
29-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
29+
with sim.write_vcd(vcd_file="test.vcd"):
3030
sim.run()
3131

3232

@@ -49,7 +49,7 @@ def process():
4949

5050
sim = Simulator(dut)
5151
sim.add_testbench(process)
52-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
52+
with sim.write_vcd(vcd_file="test.vcd"):
5353
sim.run()
5454

5555

@@ -82,7 +82,7 @@ def process():
8282
sim = Simulator(dut)
8383
sim.add_clock(1e-6)
8484
sim.add_testbench(process)
85-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
85+
with sim.write_vcd(vcd_file="test.vcd"):
8686
sim.run()
8787

8888

@@ -123,7 +123,7 @@ def process():
123123
sim = Simulator(dut)
124124
sim.add_clock(1e-6)
125125
sim.add_testbench(process)
126-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
126+
with sim.write_vcd(vcd_file="test.vcd"):
127127
sim.run()
128128

129129

@@ -164,7 +164,7 @@ def process():
164164
sim = Simulator(dut)
165165
sim.add_clock(1e-6)
166166
sim.add_testbench(process)
167-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
167+
with sim.write_vcd(vcd_file="test.vcd"):
168168
sim.run()
169169

170170

‎tests/test_csr_bus.py

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -324,7 +324,7 @@ def sim_test():
324324
sim = Simulator(dut)
325325
sim.add_clock(1e-6)
326326
sim.add_testbench(sim_test)
327-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
327+
with sim.write_vcd(vcd_file="test.vcd"):
328328
sim.run()
329329

330330

@@ -362,7 +362,7 @@ def sim_test():
362362
sim = Simulator(dut)
363363
sim.add_clock(1e-6)
364364
sim.add_testbench(sim_test)
365-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
365+
with sim.write_vcd(vcd_file="test.vcd"):
366366
sim.run()
367367

368368

@@ -463,5 +463,5 @@ def sim_test():
463463
sim = Simulator(m)
464464
sim.add_clock(1e-6)
465465
sim.add_testbench(sim_test)
466-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
466+
with sim.write_vcd(vcd_file="test.vcd"):
467467
sim.run()

‎tests/test_csr_event.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ def simulation_test(dut, process):
1212
sim = Simulator(dut)
1313
sim.add_clock(1e-6)
1414
sim.add_testbench(process)
15-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
15+
with sim.write_vcd(vcd_file="test.vcd"):
1616
sim.run()
1717

1818

‎tests/test_csr_reg.py

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -642,7 +642,7 @@ def process():
642642
sim = Simulator(dut)
643643
sim.add_clock(1e-6)
644644
sim.add_testbench(process)
645-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
645+
with sim.write_vcd(vcd_file="test.vcd"):
646646
sim.run()
647647

648648
def test_sim_single(self):
@@ -681,7 +681,7 @@ def process():
681681
sim = Simulator(dut)
682682
sim.add_clock(1e-6)
683683
sim.add_testbench(process)
684-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
684+
with sim.write_vcd(vcd_file="test.vcd"):
685685
sim.run()
686686

687687
class _MockRegister(Register, access="rw"):
@@ -1050,5 +1050,5 @@ def process():
10501050
sim = Simulator(dut)
10511051
sim.add_clock(1e-6)
10521052
sim.add_testbench(process)
1053-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
1053+
with sim.write_vcd(vcd_file="test.vcd"):
10541054
sim.run()

‎tests/test_csr_wishbone.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -151,7 +151,7 @@ def sim_test():
151151
sim = Simulator(m)
152152
sim.add_clock(1e-6)
153153
sim.add_testbench(sim_test)
154-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
154+
with sim.write_vcd(vcd_file="test.vcd"):
155155
sim.run()
156156

157157
def test_wide(self):
@@ -230,5 +230,5 @@ def sim_test():
230230
sim = Simulator(m)
231231
sim.add_clock(1e-6)
232232
sim.add_testbench(sim_test)
233-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
233+
with sim.write_vcd(vcd_file="test.vcd"):
234234
sim.run()

‎tests/test_event.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ def simulation_test(dut, process):
1212
sim = Simulator(dut)
1313
sim.add_clock(1e-6)
1414
sim.add_testbench(process)
15-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
15+
with sim.write_vcd(vcd_file="test.vcd"):
1616
sim.run()
1717

1818

‎tests/test_gpio.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -330,7 +330,7 @@ def testbench():
330330
sim = Simulator(dut)
331331
sim.add_clock(1e-6)
332332
sim.add_testbench(testbench)
333-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
333+
with sim.write_vcd(vcd_file="test.vcd"):
334334
sim.run()
335335

336336
def test_sim_without_input_sync(self):
@@ -349,5 +349,5 @@ def testbench():
349349
sim = Simulator(dut)
350350
sim.add_clock(1e-6)
351351
sim.add_testbench(testbench)
352-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
352+
with sim.write_vcd(vcd_file="test.vcd"):
353353
sim.run()

‎tests/test_wishbone_bus.py

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -283,7 +283,7 @@ def sim_test():
283283

284284
sim = Simulator(dut)
285285
sim.add_testbench(sim_test)
286-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
286+
with sim.write_vcd(vcd_file="test.vcd"):
287287
sim.run()
288288

289289
def test_addr_translate(self):
@@ -394,7 +394,7 @@ def sim_test():
394394
m.submodules += dut, loop_1, loop_2, loop_3, loop_4
395395
sim = Simulator(m)
396396
sim.add_testbench(sim_test)
397-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
397+
with sim.write_vcd(vcd_file="test.vcd"):
398398
sim.run()
399399

400400
def test_coarse_granularity(self):
@@ -416,7 +416,7 @@ def sim_test():
416416

417417
sim = Simulator(dut)
418418
sim.add_testbench(sim_test)
419-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
419+
with sim.write_vcd(vcd_file="test.vcd"):
420420
sim.run()
421421

422422

@@ -534,7 +534,7 @@ def sim_test():
534534
sim = Simulator(dut)
535535
sim.add_clock(1e-6)
536536
sim.add_testbench(sim_test)
537-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
537+
with sim.write_vcd(vcd_file="test.vcd"):
538538
sim.run()
539539

540540
def test_lock(self):
@@ -587,7 +587,7 @@ def sim_test():
587587
sim = Simulator(dut)
588588
sim.add_clock(1e-6)
589589
sim.add_testbench(sim_test)
590-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
590+
with sim.write_vcd(vcd_file="test.vcd"):
591591
sim.run()
592592

593593
def test_stall(self):
@@ -613,7 +613,7 @@ def sim_test():
613613

614614
sim = Simulator(dut)
615615
sim.add_testbench(sim_test)
616-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
616+
with sim.write_vcd(vcd_file="test.vcd"):
617617
sim.run()
618618

619619
def test_stall_compat(self):
@@ -638,7 +638,7 @@ def sim_test():
638638

639639
sim = Simulator(dut)
640640
sim.add_testbench(sim_test)
641-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
641+
with sim.write_vcd(vcd_file="test.vcd"):
642642
sim.run()
643643

644644
def test_roundrobin(self):
@@ -700,5 +700,5 @@ def sim_test():
700700
sim = Simulator(dut)
701701
sim.add_clock(1e-6)
702702
sim.add_testbench(sim_test)
703-
with sim.write_vcd(vcd_file=open("test.vcd", "w")):
703+
with sim.write_vcd(vcd_file="test.vcd"):
704704
sim.run()

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