projects/adrv9001_dual: Add READMEs and VADJ value

Signed-off-by: Elena-Hadarau_adi <Elena.Hadarau@analog.com>

Author: hadarauelena

projects/adrv9001_dual/README.md

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+# ADRV9001-DUAL HDL Project
+
+- Evaluation board product page: [ADRV9002](https://www.analog.com/eval-adrv9002)
+- System documentation: https://wiki.analog.com/resources/eval/user-guides/adrv9002/quickstart
+- HDL project documentation: https://analogdevicesinc.github.io/hdl/projects/adrv9001_dual/index.html
+- Evaluation board VADJ: 1.8V
+
+## Supported parts
+
+| Part name                                   | Description                                  |
+|---------------------------------------------|----------------------------------------------|
+| [ADRV9002](https://www.analog.com/ADRV9002) | Dual Narrow-Band and Wideband RF Transceiver |
+
+## Building the project
+
+Please enter the folder for the FPGA carrier you want to use and read the README.md.

projects/adrv9001_dual/zcu102/README.md

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+<!-- no_dts, no_no_os -->
+
+# ADRV9001-DUAL/ZCU102 HDL Project
+
+- VADJ with which it was tested in hardware: 1.8V
+
+## Building the project
+
+The parameters configurable through the `make` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration.
+
+```
+cd hdl/projects/adrv9001_dual/zcu102
+make
+```
+
+The overwritable parameters from the environment:
+
+- CMOS_LVDS_N - selects the interface type
+  - 0 = LVDS (default)
+  - 1 = CMOS
+- USE_RX_CLK_FOR_TX1 - selects the clock to drive the TX1 SSI interface
+  - 0 = TX1 dedicated clock (default)
+  - 1 = RX1 SSI clock
+  - 2 = RX2 SSI clock
+- USE_RX_CLK_FOR_TX2 - selects the clock to drive the TX2 SSI interface
+  - 0 = TX2 dedicated clock (default)
+  - 1 = RX1 SSI clock
+  - 2 = RX2 SSI clock
+
+### Example configurations
+
+#### Default configuration
+
+This specific command is equivalent to running `make` only:
+
+```
+cd hdl/projects/adrv9001_dual/zcu102
+make CMOS_LVDS_N=0
+```