diff --git a/.github/scripts/README.md b/.github/scripts/README.md index c213c59f53f..4f7a4e3c747 100644 --- a/.github/scripts/README.md +++ b/.github/scripts/README.md @@ -1,55 +1,49 @@ # Guidelines & files check scripts -These scripts are used for checking the integrity and correctness of the files across the HDL repository. The first script called **check_for_missing_readme_md.sh** is used to check the correctness of the README files only while the second script called **check_guideline.py** has the sole role of checking if our guidelines are implemented across the other files. +These scripts are used for checking the integrity and correctness of the files across the HDL repository. The first script called **check_for_missing_readme_md.sh** is used to check the correctness of the README files only while the second script called **check_guideline.py** has the sole role of checking if our guidelines are implemented across the other files. ## User guide for [check_for_missing_readme_md.sh](https://github.com/analogdevicesinc/hdl/blob/main/.github/scripts/check_for_missing_readme_md.sh) ### Prerequisites -* The script must be run from the root of the HDL repository (e.g., `/hdl`). -* It assumes a directory structure like: - * `projects//README.md`. - * `projects///README.md`. -* It requires `bash` or `sh`, but it does **not** require any external dependencies. +- The script must be run from the root of the HDL repository (e.g., `/hdl`); +- It assumes a directory structure like: + - `projects//README.md` + - `projects///README.md` +- It requires `bash` or `sh`, but it **does not** require any external dependencies. ### Purpose This script ensures that all HDL project directories contain properly formatted `README.md` files and that they follow documentation conventions. ---- - ### Rules that are checked #### 1. Presence of README files -* Each board directory (e.g., `projects/adrv9009zu11eg/`) must contain a `README.md`. -* Each carrier subdirectory (e.g., `projects/adrv9009zu11eg/zcu102/`) must also contain a `README.md`. +- Each board directory (e.g., `projects/adrv9009zu11eg/`) must contain a `README.md`; +- Each carrier subdirectory (e.g., `projects/adrv9009zu11eg/zcu102/`) must also contain a `README.md`. #### 2. Title format -* The main board README must have a title in the format:  -  ` HDL Project`  -  Example: `# ADRV9009ZU11EG HDL Project` - -* Carrier README titles must follow the format:  -  `/ HDL Project`  -  Example: `ADRV9009ZU11EG/ZCU102 HDL Project` - -* **Board names** are uppercased and underscores are replaced with hyphens (e.g., `ad9081_fmca_ebz` → `AD9081-FMCA-EBZ`). -* **Carrier names** are uppercased as-is (e.g., `de10nano` → `DE10NANO`), except for special carriers. +- The main board README must have a title in the format: ` HDL Project`. + Example: `# ADRV9009ZU11EG HDL Project`; +- Carrier README titles must follow the format: `/ HDL Project` + Example: `ADRV9009ZU11EG/ZCU102 HDL Project`; +- **Board names** are uppercased and underscores are replaced with hyphens (e.g., `ad9081_fmca_ebz` → `AD9081-FMCA-EBZ`); +- **Carrier names** are uppercased as-is (e.g., `de10nano` → `DE10NANO`), except for special carriers. #### 3. Special carrier exceptions The following carriers are allowed to use underscore in their README titles and are not flagged for title mismatches: -* `ccbob_*` -* `ccfmc_*` -* `ccpackrf_*` -* `adrv2crr_fmc` -* `adrv2crr_fmcomms8` -* `adrv2crr_fmcxmwbr1` +- `ccbob_*` +- `ccfmc_*` +- `ccpackrf_*` +- `adrv2crr_fmc` +- `adrv2crr_fmcomms8` +- `adrv2crr_fmcxmwbr1` -Based on the case, you can add special carriers by modifying the script. The difficulty of parsing so many carriers and other names is great, so it's easier to have a special-list for special carrier names. +Based on the case, you can add special carriers by modifying the script. ```sh # Function to detect special carriers (e.g., ccbob_cmos, ccfmc_lvds) @@ -67,139 +61,133 @@ is_special_carrier() { #### 4. Required sections -* **Main board README** must contain: -  - `Building the project` -  - `Supported parts` - -* **Carrier README** must contain: -  - `Building the project` -  - `Example configurations` -  - A mention of a **default configuration** under the `Example configurations` section +- **Main board README** must contain: + - `Building the project` + - `Supported parts` +- **Carrier README** must contain: + - `Building the project` + - `Example configurations` + - A mention of a **default configuration** under the `Example configurations` section #### 5. Forbidden content -* Links to the following are not allowed: +- Links to the following are not allowed: - `https://wiki.analog.com/resources/tools-software/linux-drivers-all` - `https://wiki.analog.com/linux` - -* Empty Markdown links like `` or `([ ])` are flagged. - ---- +- Empty Markdown links like `` or `([ ])` are flagged. ### Output The script prints a summary for each board and carrier, indicating: -* ✔ if the README is valid -* ✖ if there are issues, with a description of what’s missing or incorrect +- ✔ if the README is valid +- ✖ if there are issues, with a description of what’s missing or incorrect At the end, if any issues are found, it prints: **Something occurred! Check the output of the script.** ---- - -### How to run (from /hdl) +### Example of running ```sh +cd hdl/ source .github/scripts/check_for_missing_readme_md.sh ``` +--- + ## User guide for [check_guideline.py](https://github.com/analogdevicesinc/hdl/tree/main/.github/scripts/check_guideline.py) ### Prerequisites -* the script must be run while being in the root directory (/hdl) -* clean the repository to remove the files generated by Vivado -* it will be run only on Verilog files that do not contain "tb" in their path -* doesn't run on SystemVerilog files -* uses Python 3.x +- the script must be run while being in the root directory (/hdl) +- clean the repository to remove the files generated by Vivado +- it will be run only on Verilog files that do not contain "tb" in their path +- doesn't run on SystemVerilog files +- uses Python 3.x ### Rules that are checked -These rules can be found in the [HDL coding guideline](https://github.com/analogdevicesinc/hdl/blob/main/docs/hdl_coding_guideline.md). +These rules can be found in the [HDL coding guidelines](https://analogdevicesinc.github.io/hdl/user_guide/hdl_coding_guidelines.html). #### 1. License header It checks if the license header is up-to-date, containing the current year in the year range. Exceptions are the JESD files and the ones specified in the -`avoid_list` string list. +`avoid_list` string list. If `-e` option is added, the script can update the year range. #### 2. Two or more consecutive empty lines -It checks in the whole file if there are two or more consecutive empty lines. +It checks in the whole file if there are two or more consecutive empty lines. If `-e` option is added, the script can remove them and leave only one empty line. #### 3. Trailing whitespace -It checks if there are whitespace characters at the end of the lines. +It checks if there are whitespace characters at the end of the lines. If `-e` option is added, then they can be removed. #### 4. Lines after `endmodule` tag -It checks if there are lines after it. +It checks if there are lines after it. If `-e` option is added, the script can remove them. #### 5. Parentheses around the module declaration It checks if the parentheses around the module declaration (meaning `) (` for -the parameters' list) are on an empty line, right after the last parameter. +the parameters' list) are on an empty line, right after the last parameter. It also checks for the closing parenthesis at the module declaration (meaning `);`) -to be on an empty line, at the beginning, right after the last I/O port line. +to be on an empty line, at the beginning, right after the last I/O port line. If `-e` option is added, the script can put them in their proper place. #### 6. Indentation of code -It checks if all lines (except for the ones that are commented) have an indentation -of two or multiple of two spaces. -Other exceptions to this are the `module` line, the `endmodule` line, the `) (` +It checks if all lines (except for the ones that are commented) have an indentation +of two or multiple of two spaces. +Other exceptions to this are the `module` line, the `endmodule` line, the `) (` and the `);` from the module declaration. #### 7. Position of the module instances -It checks if the parameters' list (if that's the case) is in proper position, -meaning that the position of `#` is checked, the parameters to be specified each -on its own line, the parentheses around the instance name and the closing parenthesis +It checks if the parameters' list (if that's the case) is in proper position, +meaning that the position of `#` is checked, the parameters to be specified each +on its own line, the parentheses around the instance name and the closing parenthesis of the module instance. -_NOTE_: these rules are marked in the script with **GC** (stands for Guideline Check) +_NOTE_: these rules are marked in the script with **GC** (stands for Guideline Check) in the comments. ### Changes done by the script to your files If one wants the script to make changes in files, they will be regarding: -* license header, except for JESD files and the ones specified in `avoid_list` -* two or more consecutive empty lines -* trailing whitespaces -* lines after `endmodule` tag -* parentheses around the module declaration (meaning `) (` for the parameters' + +- license header, except for JESD files and the ones specified in `avoid_list` +- two or more consecutive empty lines +- trailing whitespaces +- lines after `endmodule` tag +- parentheses around the module declaration (meaning `) (` for the parameters' list and `);` for when closing the declaration) ### Ways to run the script -1. With no arguments: `python3 check_guideline.py` -Checks all files with the properties specified above. +1. With no arguments: `python3 check_guideline.py` +Checks all files with the properties specified above. Does not modify the files. 2. With arguments: - 1. `-e` with no file specified - Checks all files with the properties specified above. Additionally, - it modifies the module definition parentheses according to the guideline. - - 2. `-m` - Checks files that are given as arguments (by their names including the - extension). - - 3. `-me` - Checks files that are given as arguments (by their names including the - extension) and modifies the files where the guideline is not respected. - - 4. `-p` - Checks files that are given as arguments (by their relative path) and - modifies the files where the guideline is not respected. - - 5. `-pe` - Checks files that are given as arguments (by their relative path) and - modifies the files where the guideline is not respected. + 1. `-e` with no file specified + Checks all files with the properties specified above. Additionally, + it modifies the module definition parentheses according to the guideline. + 2. `-m` + Checks files that are given as arguments (by their names including the + extension). + 3. `-me` + Checks files that are given as arguments (by their names including the + extension) and modifies the files where the guideline is not respected. + 4. `-p` + Checks files that are given as arguments (by their relative path) and + modifies the files where the guideline is not respected. + 5. `-pe` + Checks files that are given as arguments (by their relative path) and + modifies the files where the guideline is not respected. ### Examples of running diff --git a/docs/projects/ad9081_fmca_ebz/index.rst b/docs/projects/ad9081_fmca_ebz/index.rst index d97a5fe67e5..77a909ca574 100644 --- a/docs/projects/ad9081_fmca_ebz/index.rst +++ b/docs/projects/ad9081_fmca_ebz/index.rst @@ -471,75 +471,30 @@ SPI connections GPIOs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. list-table:: - :widths: 25 20 20 20 15 - :header-rows: 2 - - * - GPIO signal - - Direction - - HDL GPIO EMIO - - Software GPIO - - Software GPIO - * - - - (from FPGA view) - - - - Zynq-7000 - - Zynq MP - * - txen[1:0] - - OUT - - 59:58 - - 113:112 - - 137:136 - * - rxen[1:0] - - OUT - - 57:56 - - 111:110 - - 135:134 - * - rstb - - OUT - - 55 - - 109 - - 133 - * - hmc_sync - - OUT - - 54 - - 108 - - 132 - * - irqb[1:0] - - IN - - 53:52 - - 107:106 - - 131:130 - * - agc3[1:0] - - IN - - 51:50 - - 105:104 - - 129:128 - * - agc2[1:0] - - IN - - 49:48 - - 103:102 - - 127:126 - * - agc1[1:0] - - IN - - 47:46 - - 101:100 - - 125:124 - * - agc0[1:0] - - IN - - 45:44 - - 99:98 - - 123:122 - * - hmc_gpio1 - - INOUT - - 43 - - 97 - - 121 - * - gpio[10:0] - - INOUT - - 42:32 - - 96:86 - - 120:110 +=========== ========= ======= ========= =================== ====== +GPIO signal Direction HDL no. Zynq-7000 Zynq UltraScale+ MP Versal +=========== ========= ======= ========= =================== ====== +txen[1:0] OUT 59:58 113:112 137:136 27:26 +rxen[1:0] OUT 57:56 111:110 135:134 25:24 +rstb OUT 55 109 133 23 +hmc_sync OUT 54 108 132 22 +irqb[1:0] IN 53:52 107:106 131:130 21:20 +agc3[1:0] IN 51:50 105:104 129:128 19:18 +agc2[1:0] IN 49:48 103:102 127:126 17:16 +agc1[1:0] IN 47:46 101:100 125:124 15:14 +agc0[1:0] IN 45:44 99:98 123:122 13:12 +hmc_gpio1 INOUT 43 97 121 11 +gpio[10:0] INOUT 42:32 96:86 120:110 10:0 +=========== ========= ======= ========= =================== ====== + +.. admonition:: Legend + :class: note + + - GPIO signal = name of the GPIO in the HDL project + - Direction = from the FPGA point of view + - HDL no. = HDL GPIO EMIO + - Zynq-7000, Zynq UltraScale+ MP, Versal are Software GPIOs, to be used in + device trees Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9209_fmca_ebz/index.rst b/docs/projects/ad9209_fmca_ebz/index.rst index ef77bc84288..996178296fc 100644 --- a/docs/projects/ad9209_fmca_ebz/index.rst +++ b/docs/projects/ad9209_fmca_ebz/index.rst @@ -171,58 +171,28 @@ SPI connections GPIOs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. list-table:: - :widths: 25 25 25 25 - :header-rows: 2 - - * - GPIO signal - - Direction - - HDL GPIO EMIO - - Software GPIO - * - - - (from FPGA view) - - - - Versal - * - rxen[1:0] - - OUT - - 57:56 - - 135:134 - * - rstb - - OUT - - 55 - - 133 - * - hmc_sync - - OUT - - 54 - - 132 - * - irqb[1:0] - - IN - - 53:52 - - 131:130 - * - agc3[1:0] - - IN - - 51:50 - - 129:128 - * - agc2[1:0] - - IN - - 49:48 - - 127:126 - * - agc1[1:0] - - IN - - 47:46 - - 125:124 - * - agc0[1:0] - - IN - - 45:44 - - 123:122 - * - hmc_gpio1 - - INOUT - - 43 - - 121 - * - gpio[10:0] - - INOUT - - 42:32 - - 120:110 +=========== ========= ======= ======= +GPIO signal Direction HDL no. Versal +=========== ========= ======= ======= +rxen[1:0] OUT 57:56 25:24 +rstb OUT 55 23 +hmc_sync OUT 54 22 +irqb[1:0] IN 53:52 21:20 +agc3[1:0] IN 51:50 19:18 +agc2[1:0] IN 49:48 17:16 +agc1[1:0] IN 47:46 15:14 +agc0[1:0] IN 45:44 13:12 +hmc_gpio1 INOUT 43 11 +gpio[10:0] INOUT 42:32 10:0 +=========== ========= ======= ======= + +.. admonition:: Legend + :class: note + + - GPIO signal = name of the GPIO in the HDL project + - Direction = from the FPGA point of view + - HDL no. = HDL GPIO EMIO + - Versal = Software GPIOs, to be used in device trees Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9467_fmc/ad9467_fmc_block_diagram.svg b/docs/projects/ad9467_fmc/ad9467_fmc_block_diagram.svg index dea5c876559..d4fb366404c 100755 --- a/docs/projects/ad9467_fmc/ad9467_fmc_block_diagram.svg +++ b/docs/projects/ad9467_fmc/ad9467_fmc_block_diagram.svg @@ -2,23 +2,22 @@ + inkscape:version="1.4 (86a8ad7, 2024-10-11)" + sodipodi:docname="ad9467_fmc_block_diagram.svg" + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" + xmlns:xlink="http://www.w3.org/1999/xlink" + xmlns="http://www.w3.org/2000/svg" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" + xmlns:cc="http://creativecommons.org/ns#" + xmlns:dc="http://purl.org/dc/elements/1.1/"> @@ -48,7 +47,7 @@ @@ -63,7 +62,7 @@ @@ -80,7 +79,7 @@ inkscape:connector-curvature="0" id="path4660-1" d="M 5.77,0 -2.88,5 V -5 Z" - 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xml:space="preserve"> + xml:space="preserve" /> Timer MEMORY INTERCONNECT + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:16px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial, Bold';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:1px">MEMORY INTERCONNECT KC705Zed FMC CONNECTOR + x="-231.01797" + y="640.97186" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:16px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial, Bold';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:1px">FMC CONNECTOR AD9467_DMA DMA_Clk DMA_Clk=100MHz LVDS INTERFACE ADC_Clk =250MHz + x="317.72675" + y="298.50735" + style="stroke-width:1" + id="tspan5125"> ADC_Clk=250MHz + style="display:inline;opacity:1;fill:#4cbeef;fill-opacity:0;fill-rule:nonzero;stroke:#a01414;stroke-width:1.92205;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new"> DAC core frame AD9467 CORE + sodipodi:role="line">AXI AD9467 IP CORE ADC CHANNEL + xml:space="preserve" /> RX[7:0]_P + x="500" + y="81.094482">ADC_DATA_IN_P[7:0] RX[7:0]_N + x="500" + y="104.09447">ADC_DATA_IN_N[7:0] CLK_IN_P + x="499.99957" + y="145.09448">ADC_CLK_IN_P CLK_IN_N + x="499.99957" + y="168.09448">ADC_CLK_IN_N DATA_OR_P + x="499.99957" + y="207.09448">ADC_DATA_OR_P DATA_OR_N + x="499.99957" + y="233.09448">ADC_DATA_OR_N @@ -1153,9 +1140,9 @@ inkscape:connector-curvature="0" id="path8424" d="M 406.04958,430.92913 H 404.6091" - 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style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.06700003;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.067;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> @@ -1198,7 +1185,7 @@ inkscape:connector-curvature="0" id="path8450" d="M 406.04958,428.80003 H 404.6091" - style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.06700003;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.067;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.33851;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.2;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.2;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.973;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.308598;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.308598;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.308598;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="display:inline;stroke-width:2.41103;stroke-miterlimit:4;stroke-dasharray:none;shape-rendering:crispEdges;enable-background:new"> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#a01414;stroke-width:0.841327;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="display:inline;opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#a01414;stroke-width:0.821852;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> IQ Corr @@ -1521,7 +1508,7 @@ cy="607.36047" cx="398.48099" id="circle5525" - style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.39996076;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.39996;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" r="0.80001962" /> + style="display:inline;opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#a01414;stroke-width:0.841327;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> DC ` captures +and buffers data from the ADC. The DMA interface then transfers the samples +to the external DDR-DRAM. The capture is initiated by the software. The status +of capture (overflow, over the range) are reported back to the software. Clock selection ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -117,7 +118,7 @@ A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the AD9517. - Populate (C304, C305) for LVPECL clock driver **or** (C306, C307) for - LVDS clock driver, with 0.1 µF capacitors + LVDS clock driver, with 0.1 µF capacitors - Remove C209 and C210 to disconnect the default clock path inputs The :adi:`AD9517` has many SPI-selectable options that are set to a default @@ -161,6 +162,10 @@ Depending on the carrier, the SPI connections are as follows: - spi0 - AD9467 - 0 + * - PS + - spi0 + - AD9517-4 + - 1 * - MicroBlaze - spi_* - AD9467 @@ -212,10 +217,10 @@ Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Product datasheet: :adi:`AD9467` -- The schematic of the board can be found - :dokuwiki:`here <_media/resources/fpga/xilinx/fmc/02-041710-01-c-1.pdf>`, - or :dokuwiki:`here <_media/resources/fpga/xilinx/fmc/9467fmc01c_sch.pdf>` - for older versions. +- The schematic of the new board can be found + :dokuwiki:`here <_media/resources/fpga/xilinx/fmc/02-041710-01-c-1.pdf>` + (for older versions, + :dokuwiki:`here <_media/resources/fpga/xilinx/fmc/9467fmc01c_sch.pdf>`) HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -238,13 +243,13 @@ HDL related * - AXI_DMAC - :git-hdl:`library/axi_dmac` - :ref:`axi_dmac` - * - AXI_HDMI_TX + * - AXI_HDMI_TX * - :git-hdl:`library/axi_hdmi_tx` - :ref:`axi_hdmi_tx` - * - AXI_I2S_ADI + * - AXI_I2S_ADI * - :git-hdl:`library/axi_i2s_adi` - --- - * - AXI_SPDIF_TX + * - AXI_SPDIF_TX * - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID @@ -253,18 +258,24 @@ HDL related * - SYSID_ROM - :git-hdl:`library/sysid_rom` - :ref:`axi_sysid` - * - UTIL_I2C_MIXER + * - UTIL_I2C_MIXER * - :git-hdl:`library/util_i2c_mixer` - --- +.. admonition:: Legend + :class: note + + - ``*`` instantiated only for Zedboard + Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-linux:`AD9467-FMC KC705 Linux device tree ` +- :git-linux:`AD9467-FMC KC705 Linux device tree (2023_R2 release) <2023_R2:arch/microblaze/boot/dts/kc705_ad9467_fmc.dts>` - :git-linux:`AD9467-FMC ZedBoard Linux device tree zynq-zed-adv7511-ad9467-fmc-250ebz.dts ` - :git-linux:`Linux driver ad9467.c ` - :dokuwiki:`[Wiki] AD9467-FMC on ZedBoard using ACE ` -- :git-no-os:`No-OS project ` and :git-no-os:`No-OS driver ` +- :git-no-os:`AD9467 no-OS project ` and + :git-no-os:`AD9467 no-OS driver ` .. include:: ../common/more_information.rst diff --git a/docs/user_guide/architecture.rst b/docs/user_guide/architecture.rst index 6b918ef8806..686f815b37d 100644 --- a/docs/user_guide/architecture.rst +++ b/docs/user_guide/architecture.rst @@ -248,7 +248,8 @@ from the HDL project to obtain the final number used in software: - PS7 EMIO offset = **54** - PS8 EMIO offset = **78** -- MicroBlaze - no offset +- MicroBlaze offset = **no offset** +- Versal offset = **-32** Connectivity ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/user_guide/build_boot_bin.rst b/docs/user_guide/build_boot_bin.rst index 2521bc726fe..acd43e83ad1 100644 --- a/docs/user_guide/build_boot_bin.rst +++ b/docs/user_guide/build_boot_bin.rst @@ -25,13 +25,16 @@ project) and ``u-boot.elf`` (from the SD card with Kuiper image). Check the :ref:`Enviroment ` section of :ref:`build_hdl`. +As prerequisites, you need to have ``xlsclients`` from the ``x11-utils`` package +installed in your Linux/WSL system. + .. _build_boot_bin zynq: For Zynq ------------------------------------------------------------------------------- This section applies to the Zynq-based carriers from -:ref:`our list `, but not limited to them only. +:ref:`our list `. Make sure that AMD Xilinx Vivado and Vitis are included in the path and a cross-compiler for ``arm`` exists before running the script. @@ -58,8 +61,14 @@ The script can take 3 parameters: See the beginning of :external+documentation:ref:`kuiper sdcard` for instructions on how to obtain the ADI Kuiper image. -The script can be saved in the folder local to the project (for -example, hdl/projects/fmcomms2/zed) and to be run from there. +If you didn't use ``make`` parameters when building the project, then +the script can be saved in the **folder local to the project** (for +example, hdl/projects/$ADI_PART/$CARRIER) and **to be run from there**. + +If you did use ``make`` parameters, then you need to go to the build folder +that was created based on the parameters you gave, +(would look like this hdl/projects/$ADI_PART/$CARRIER/$param1_param2), +save it there and **run it from there**. .. shell:: bash @@ -69,7 +78,11 @@ example, hdl/projects/fmcomms2/zed) and to be run from there. The build output (``BOOT.BIN``) can be found in the local directory ``output_boot_bin`` where you ran the command. -The folder follows the pattern: *hdl/projects/$ADI_PART/$CARRIER/output_boot_bin*. + +The folder follows the following pattern if ``make`` parameters were not used +*hdl/projects/$ADI_PART/$CARRIER/output_boot_bin*, and this pattern if +parameters were used +*hdl/projects/$ADI_PART/$CARRIER/$PARAM1_PARAM2/output_boot_bin*. .. _build_boot_bin zynqmp: @@ -106,6 +119,15 @@ The script can take 4 parameters (the last one is optional): See the beginning of :external+documentation:ref:`kuiper sdcard` for instructions on how to obtain the ADI Kuiper image. +If you didn't use ``make`` parameters when building the project, then +the script can be saved in the **folder local to the project** (for +example, hdl/projects/$ADI_PART/$CARRIER) and **to be run from there**. + +If you did use ``make`` parameters, then you need to go to the build folder +that was created based on the parameters you gave, +(would look like this hdl/projects/$ADI_PART/$CARRIER/$param1_param2), +save it there and **run it from there**. + .. shell:: bash $cd hdl/projects/fmcomms2/zcu102 @@ -114,7 +136,10 @@ The script can take 4 parameters (the last one is optional): The build output (``BOOT.BIN``) can be found in the local directory ``output_boot_bin`` where you ran the command. -The folder follows the pattern: *hdl/projects/$ADI_PART/$CARRIER/output_boot_bin*. +The folder follows the following pattern if ``make`` parameters were not used +*hdl/projects/$ADI_PART/$CARRIER/output_boot_bin*, and this pattern if +parameters were used +*hdl/projects/$ADI_PART/$CARRIER/$PARAM1_PARAM2/output_boot_bin*. .. _build_boot_bin versal: @@ -151,6 +176,15 @@ The script can take 4 parameters: See the beginning of :external+documentation:ref:`kuiper sdcard` for instructions on how to obtain the ADI Kuiper image. +If you didn't use ``make`` parameters when building the project, then +the script can be saved in the **folder local to the project** (for +example, hdl/projects/$ADI_PART/$CARRIER) and **to be run from there**. + +If you did use ``make`` parameters, then you need to go to the build folder +that was created based on the parameters you gave, +(would look like this hdl/projects/$ADI_PART/$CARRIER/$param1_param2), +save it there and **run it from there**. + .. shell:: bash $cd hdl/projects/ad9081_fmca_ebz/vck190 @@ -159,7 +193,11 @@ The script can take 4 parameters: The build output (``BOOT.BIN``) can be found in the local directory ``output_boot_bin`` where you ran the command. -The folder follows the pattern: *hdl/projects/$ADI_PART/$CARRIER/output_boot_bin*. +The folder follows the following pattern if ``make`` parameters were not used +*hdl/projects/$ADI_PART/$CARRIER/output_boot_bin*, and this pattern if +parameters were used +*hdl/projects/$ADI_PART/$CARRIER/$PARAM1_PARAM2/output_boot_bin*. + More information ------------------------------------------------------------------------------- diff --git a/docs/user_guide/build_hdl.rst b/docs/user_guide/build_hdl.rst index 83aa5871271..94cd2094c63 100644 --- a/docs/user_guide/build_hdl.rst +++ b/docs/user_guide/build_hdl.rst @@ -55,23 +55,30 @@ be described: 1. Needed tools ------------------------------------------------------------------------------- -#. Install the required FPGA design suite. We use `AMD Xilinx Vivado`_, - `Intel Quartus Prime Pro and Standard`_, `Lattice Radiant`_ and - `Lattice Propel`_. - You can find information about the proper version in the section - :ref:`build_hdl tool-versions`. - Make sure that you're always using the latest release. +We offer reference designs for our evaluation boards, on three FPGA platforms: +from AMD Xilinx, from Intel and from Lattice. + +Each one of these platforms has their own FPGA design suites: + +- AMD Xilinx with `AMD Xilinx Vivado and Vitis`_ (HDL and software) +- Intel with `Intel Quartus Prime Pro and Standard`_ +- Lattice with `Lattice Radiant`_ and `Lattice Propel`_ + #. The **required** Vivado/Quartus/Propel/Radiant version can be found in: - - :git-hdl:`scripts/adi_env.tcl` - - or in the `release notes `__ + - :git-hdl:`scripts/adi_env.tcl` + - or in the `release notes `__ + + More details can be found at :ref:`build_hdl tool-versions`. + Make sure that you're always using the latest release. -#. Download the tools from the following links: +#. Download and install the **Linux version** of the FPGA design suite that + you want to use, from the following links: - - :xilinx:`AMD tools ` + - :xilinx:`AMD tools ` * (make sure you're downloading the proper installer. For full installation, it is better to choose the one that downloads - and installs both Vivado and Vitis at the same time) + and installs **both Vivado and Vitis** at the same time) - :intel:`Intel tools ` - `Lattice tools `__ @@ -82,6 +89,12 @@ be described: `GNU Make `__ to build the projects. Depending on what OS you're using, you have these options: +.. admonition:: Legend + + \* - the Linux version is required for the tools, because even if you're OS + is Windows, you need to use WSL and install the tools under WSL (Windows + Subsystem for Linux). + .. _build_hdl setup-repo: 2. Setup the HDL repository @@ -101,7 +114,8 @@ If you want to build the sources, ADI makes them available on the `clone `__ the repository. This is the best method to get the sources. -Here, we are cloning the repository inside a directory called **adi**. +Here, we are cloning the repository inside the home directory of your Linux +file system. Please refer to the :ref:`git_repository` section for more details. Cloning is now done using HTTPS and a classic PAT (Personal Access Token). @@ -110,7 +124,9 @@ More details on how to do this, .. shell:: bash + ~/ $git clone https://github.com/analogdevicesinc/hdl.git + $cd hdl If you use WSL, you must clone your HDL repository in the WSL file system. For example ``\\wsl.localhost\Ubuntu\home\username\hdl``. @@ -169,6 +185,7 @@ for the current session (or open a new one) and call the defined method: .. shell:: bash + ~/hdl $source ~/.bashrc $load_amd @@ -190,10 +207,10 @@ For AMD Xilinx Vivado: .. shell:: bash ~/hdl - $source /opt/Xilinx/Vivado/202x.x/settings64.sh + $source /opt/Xilinx/Vivado/2023.2/settings64.sh - $export PATH=$PATH:/opt/Xilinx/Vivado/202x.x/bin:/opt/Xilinx/Vitis/202x.x/bin - $export PATH=$PATH:/opt/Xilinx/Vitis/202x.x/gnu/microblaze/nt/bin + $export PATH=$PATH:/opt/Xilinx/Vivado/2023.2/bin:/opt/Xilinx/Vitis/2023.2/bin + $export PATH=$PATH:/opt/Xilinx/Vitis/2023.2/gnu/microblaze/nt/bin For Intel Quartus: @@ -207,8 +224,8 @@ For Lattice: .. shell:: bash ~/hdl - $export PATH=$PATH:/opt/lscc/propel/202x.x/builder/rtf/bin/lin64 - $export PATH=$PATH:/opt/lscc/radiant/202x.x/bin/lin64 + $export PATH=$PATH:/opt/lscc/propel/2023.2/builder/rtf/bin/lin64 + $export PATH=$PATH:/opt/lscc/radiant/2023.2/bin/lin64 3b. Windows environment setup ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -258,13 +275,13 @@ In the link above, you can find the installation guide for WSL on Windows. .. collapsible:: How to install the tools in WSL Before building any project, - :red:`it is necessary to install the Linux version for Vivado, in the WSL file system`, - because on the Ubuntu distribution on WSL you cannot - run projects from on the Windows version of them. When you have to choose - the installation path, choose the location where WSL is installed - ``\\wsl.localhost\Ubuntu\opt``. + :red:`it is necessary to install the Linux version for Vivado & Vitis, in the WSL file system`, + because on the Ubuntu distribution on WSL you cannot run projects from on + the Windows version of them. When you have to choose + the installation path, choose the location where WSL is installed, in its + /opt folder ``\\wsl.localhost\Ubuntu\opt``. - Also, to get the best performance, you must clone your HDL repository in + Also, to get the best performance, you **must clone** your HDL repository in the WSL file system. For example: ``\\wsl.localhost\Ubuntu\home\username\hdl``. For more information you can consult the following link: @@ -279,10 +296,13 @@ In the link above, you can find the installation guide for WSL on Windows. $chmod +x FPGAs_AdaptiveSoCs_Unified_2023.2_1113_1001_Lin64.bin $sudo ./FPGAs_AdaptiveSoCs_Unified_2023.2_1113_1001_Lin64.bin + The installation directory for AMD Xilinx Vivado & Vitis we chose to be + ``/opt/Xilinx``. + Now, you may have noticed that the installation raised a couple of warnings, such as: - .. code-block:: + .. shell:: bash $/tools/Xilinx/Vivado/2023.2/bin/rdiArgs.sh: line 31: warning: setlocale: LC_ALL: cannot change locale (en_US.UTF-8): No such file or directory /bin/bash: warning: setlocale: LC_ALL: cannot change locale (en_US.UTF-8) @@ -302,25 +322,27 @@ In the link above, you can find the installation guide for WSL on Windows. $cd /opt/Xilinx/Vitis/2023.2/scripts $sudo ./installLibs.sh $sudo apt-get install libxrender1 libxtst6 libxi6 - $sudo apt-get install libtinfo5 # to be used only in case you have issues with missing libtinfo5 when building a project + $sudo apt-get install libtinfo5 + $wget http://security.ubuntu.com/ubuntu/pool/universe/n/ncurses/libtinfo5_6.3-2ubuntu0.1_amd64.deb + $sudo apt install ./libtinfo5_6.3-2ubuntu0.1_amd64.deb Then you need to add the following paths to your $PATH environment variable: .. shell:: bash - $export PATH=$PATH:/opt/path_to/Xilinx/Vivado/202x.x/bin - $export PATH=$PATH:/opt/path_to/Xilinx/Vivado_HLS/202x.x/bin + $export PATH=$PATH:/opt/Xilinx/Vivado/2023.2/bin + $export PATH=$PATH:/opt/Xilinx/Vivado_HLS/2023.2/bin - $export PATH=$PATH:/opt/path_to/Xilinx/Vitis/202x.x/bin - $export PATH=$PATH:/opt/path_to/Xilinx/Vitis/202x.x/gnu/microblaze/nt/bin - $export PATH=$PATH:/opt/path_to/Xilinx/Vitis/202x.x/gnu/arm/nt/bin - $export PATH=$PATH:/opt/path_to/Xilinx/Vitis/202x.x/gnu/microblaze/linux_toolchain/nt64_be/bin - $export PATH=$PATH:/opt/path_to/Xilinx/Vitis/202x.x/gnu/microblaze/linux_toolchain/nt64_le/bin - $export PATH=$PATH:/opt/path_to/Xilinx/Vitis/202x.x/gnu/aarch32/nt/gcc-arm-none-eabi/bin + $export PATH=$PATH:/opt/Xilinx/Vitis/2023.2/bin + $export PATH=$PATH:/opt/Xilinx/Vitis/2023.2/gnu/microblaze/nt/bin + $export PATH=$PATH:/opt/Xilinx/Vitis/2023.2/gnu/arm/nt/bin + $export PATH=$PATH:/opt/Xilinx/Vitis/2023.2/gnu/microblaze/linux_toolchain/nt64_be/bin + $export PATH=$PATH:/opt/Xilinx/Vitis/2023.2/gnu/microblaze/linux_toolchain/nt64_le/bin + $export PATH=$PATH:/opt/Xilinx/Vitis/2023.2/gnu/aarch32/nt/gcc-arm-none-eabi/bin -.. collapsible:: Alternatives to Cygwin/WSL/Linux terminal +.. collapsible:: Alternatives to WSL/Linux terminal - If you do not want to use neither Cygwin nor WSL, there might still be some + If you do not want to use WSL/Linux/Cygwin, there might still be some alternative. There are ``make`` alternatives for **Windows Command Prompt**, minimalist GNU for Windows (**MinGW**), or the **Cygwin variations** installed by the tools itself. @@ -329,7 +351,7 @@ In the link above, you can find the installation guide for WSL on Windows. Some of these may not be fully functional with our scripts and/or projects. If you are an Intel user, the **Nios II Command Shell** does support make. If you are an AMD user, use the **gnuwin** installed as part of the SDK, - usually at ``C:\Xilinx\Vitis\202x.x\gnuwin\bin``. + usually at ``C:\Xilinx\Vitis\2023.2\gnuwin\bin``. **How to verify your environment setup** @@ -373,14 +395,14 @@ the Vivado Tcl console building mode to build the BOOT.BIN (see .. shell:: bash ~/hdl - $export PATH=$PATH:/cygdrive/c/Xilinx/Vivado/202x.x/bin - $export PATH=$PATH:/cygdrive/c/Xilinx/Vivado_HLS/202x.x/bin - $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/bin - $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/microblaze/nt/bin - $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/arm/nt/bin - $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/microblaze/linux_toolchain/nt64_be/bin - $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/microblaze/linux_toolchain/nt64_le/bin - $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/aarch32/nt/gcc-arm-none-eabi/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vivado/2023.2/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vivado_HLS/2023.2/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/2023.2/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/2023.2/gnu/microblaze/nt/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/2023.2/gnu/arm/nt/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/2023.2/gnu/microblaze/linux_toolchain/nt64_be/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/2023.2/gnu/microblaze/linux_toolchain/nt64_le/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/2023.2/gnu/aarch32/nt/gcc-arm-none-eabi/bin For Intel Quartus: @@ -394,8 +416,8 @@ the Vivado Tcl console building mode to build the BOOT.BIN (see .. shell:: bash ~/hdl - $export PATH=$PATH:/cygdrive/c/lscc/propel/202x.x/builder/rtf/bin/nt64 - $export PATH=$PATH:/cygdrive/c/lscc/radiant/202x.x/bin/nt64 + $export PATH=$PATH:/cygdrive/c/lscc/propel/2023.2/builder/rtf/bin/nt64 + $export PATH=$PATH:/cygdrive/c/lscc/radiant/2023.2/bin/nt64 .. collapsible:: Building the libraries and the project in Vivado GUI @@ -488,7 +510,7 @@ in hardware using the Vivado version :ref:`specific for that branch `. Simply put, to build a project you just run ``make`` in your Linux terminal -or in Cygwin. For more details, please read the rest of the documentation. +or in WSL. For more details, please read the rest of the documentation. To clean only a project or an IP core before building it again, run ``make clean``. @@ -502,7 +524,7 @@ project, run ``make clean-all``. An AMD project is built the same way as an Intel project. The only exception is that there are a few 'sub-make(s)' for the library -components. The way of building a project in Cygwin and WSL is almost the same. +components. You just need to go to the hdl/projects folder, choose the ADI part that you want to use, then enter the folder of the FPGA carrier that you want, and run @@ -897,7 +919,7 @@ The **sof** file is used to program the device. .. warning:: Instantiating IPs in Propel Builder CLI or GUI does not work in WSL for an - unknown compatibility reason. You can use Cygwin on Windows or a normal + unknown compatibility reason. You can use WSL/Cygwin on Windows or a normal Linux installation. .. warning:: @@ -1308,7 +1330,7 @@ ignored, they won't affect the functionality of the IP or the project. However, you may not be able to archive these projects. The irony is that it does copy these files to the project area, but ignores them. -.. _AMD Xilinx Vivado: https://www.xilinx.com/support/download.html +.. _AMD Xilinx Vivado and Vitis: https://www.xilinx.com/support/download.html .. _Intel Quartus Prime Pro and Standard: https://www.intel.com/content/www/us/en/products/details/fpga/development-tools/quartus-prime/resource.html diff --git a/projects/ad9082_fmca_ebz/zcu102/README.md b/projects/ad9082_fmca_ebz/zcu102/README.md index 82c44317a57..d8fe31d7fe8 100644 --- a/projects/ad9082_fmca_ebz/zcu102/README.md +++ b/projects/ad9082_fmca_ebz/zcu102/README.md @@ -52,7 +52,7 @@ TX_NUM_LINKS=1 Corresponding device tree: [zynqmp-zcu102-rev10-ad9082-m4-l8.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9082-m4-l8.dts) -#### JESD24C, TX mode 20, RX mode 19, subclass 1 +#### JESD204C, TX mode 20, RX mode 19, subclass 1 ``` make JESD_MODE=64B66B \