@@ -3364,6 +3364,7 @@ void Capstone2LlvmIrTranslatorX86_impl::translateShiftX(cs_insn* i, cs_x86* xi,
33643364 case X86_INS_SHR: return llvm::Instruction::BinaryOps::LShr;
33653365 case X86_INS_SAR: return llvm::Instruction::BinaryOps::AShr;
33663366 case X86_INS_SHL: return llvm::Instruction::BinaryOps::Shl;
3367+ default : assert (false );
33673368 }
33683369 }();
33693370
@@ -5442,5 +5443,28 @@ void Capstone2LlvmIrTranslatorX86_impl::translateRdtscp(cs_insn* i, cs_x86* xi,
54425443 storeRegister (X86_REG_ECX, irb.CreateExtractValue (c, {2 }), irb);
54435444}
54445445
5446+ void Capstone2LlvmIrTranslatorX86_impl::translateTzcntOrLzcnt (cs_insn* i, cs_x86* xi, llvm::IRBuilder<>& irb)
5447+ {
5448+ EXPECT_IS_BINARY (i, xi, irb);
5449+
5450+ std::tie (op0, op1) = loadOpBinary (xi, irb);
5451+
5452+ storeRegister (X86_REG_CF, generateZeroFlag (op1, irb), irb);
5453+
5454+ op0 = irb.CreateIntrinsic (
5455+ i->id == X86_INS_LZCNT ? llvm::Intrinsic::ctlz : llvm::Intrinsic::cttz,
5456+ {op1->getType ()},
5457+ {op1, irb.getFalse ()});
5458+
5459+ storeRegister (X86_REG_OF, irb.getFalse (), irb); // undef
5460+ storeRegister (X86_REG_SF, irb.getFalse (), irb); // undef
5461+ storeRegister (X86_REG_PF, irb.getFalse (), irb); // undef
5462+ storeRegister (X86_REG_AF, irb.getFalse (), irb); // undef
5463+
5464+ storeRegister (X86_REG_ZF, generateZeroFlag (op0, irb), irb);
5465+
5466+ storeOp (xi->operands [0 ], op0, irb);
5467+ }
5468+
54455469} // namespace capstone2llvmir
54465470} // namespace retdec
0 commit comments