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How to use RV's outer loop vectorizer in your LLVM frontend
RV ships with an outer loop vectorizer pass. The vectorizer pass needs loop metadata to detect vectorizable loops. We lay out the steps below.
Add RV's outer-loop vectorizer to your pass pipeline with rv::addOuterLoopVectorizer(PM) (declared in passes.h).
RV will vectorize arbitrary reducible control inside the outer loops you want to vectorize. However, every loop that shall be vectorized needs to be a simple counting loop. Further, the loop needs to have a unique latch exit. That is, there is a unique latch block and the latch block contains the only loop exit of the loop.
RV's outer-loop vectorizer relies on metadata hints to detect vectorizable loops. These have the following structure:
; module level metadata
!11 = distinct !{!11, !12, !13, !14}
!12 = !{!"llvm.loop.vectorize.enable", i1 true}
!13 = !{!"llvm.loop.vectorize.width", i32 16}
; named medata on the latch terminator
def foo {
...
; terminator of loop latch
br i1 %exitcond, label %for.body.exit, label %for.body.header !llvm.loop !11
...
}
This metadata tells RV that the loop can be vectorized (llvm.loop.vectorize.enable) and that the maximal vectorization factor for this loop is 16 (llvm.loop.vectorize.width). This is the same format used by Clang to communicate vectorization hints to LLVM's loop vectorizer.
RV can automatically use fast SIMD math functions of the SLEEF vector math library. To enable this feature, RV needs to know the SIMD ISA extensions that your target supports. This is done by setting the appropriate flags in the rv::Config object that is passed to rv::addOuterLoopVectorizer(PM, config). For example, if your target is a machine with AVX2, set "config.useAVX2 = true".
RV has an integrated reduction analysis for value reductions (data-typed header phi nodes). Use rv::SetReductionHint(loopHeaderPhi, redKind) to set the reduction kind of a loop header phi. Reduction hints take precedence over automatic inference.