Merge pull request #2188 from aavdiere/master

[LINT] Allow interconnection net or port (Syntax 6-2)

Author: hzeller

verilog/parser/verilog.y

@@ -5586,9 +5586,10 @@ net_declaration
                           MakePackedDimensionsNode($3),
                           $5, $6); }
   | net_type delay3 net_variable_or_decl_assigns ';'
-  { $$ = MakeTaggedNode(N::kNetDeclaration, MakeDataType(nullptr, $1, $2, nullptr), nullptr, nullptr, $3, $4); }
+    { $$ = MakeTaggedNode(N::kNetDeclaration, MakeDataType(nullptr, $1, $2, nullptr), nullptr, nullptr, $3, $4); }
   /* TODO(fangism): net_type_identifer [ delay_control ] list_of_net_decl_assignments */
-  /* TODO(fangism): TK_interconnect ... */
+  | TK_interconnect net_variable_or_decl_assigns ';'
+    { $$ = MakeTaggedNode(N::kNetDeclaration, MakeDataType($1), nullptr, $2, $3); }
   ;
 
 module_port_declaration