Skip to content

the output of pcm-iio on EMR may not be correct #946

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wangyi4 opened this issue Apr 28, 2025 · 8 comments
Open

the output of pcm-iio on EMR may not be correct #946

wangyi4 opened this issue Apr 28, 2025 · 8 comments
Labels

Comments

@wangyi4
Copy link

wangyi4 commented Apr 28, 2025

I ran pcm-iio on EMR6554s. It seems the output from pcm-iio program is not correct. QAT are connected to PCIe1 and PCIe4.

|IIO Stack 4 - PCIe1 |
|0000:6F:01.0|Gen0 x0 |8086:0B25 Intel Corporation unknown device; Part: 0, 1, 2, ��
|0000:70:00.0|Gen1 x1 |8086:4940 Intel Corporation 4xxx Series QAT; Part: 4, ��
|0000:72:00.0|Gen0 x0 |8086:2710 Intel Corporation unknown device; Part: 5, ��


|IIO Stack 9 - PCIe4|
|0000:79:01.0|Gen0 x0 |8086:0B25 Intel Corporation unknown device; Part: 0, 1, 2, ��
|0000:7A:00.0|Gen1 x1 |8086:4940 Intel Corporation 4xxx Series QAT; Part: 4, ��
|0000:7C:00.0|Gen0 x0 |8086:2710 Intel Corporation unknown device; Part: 5, ��

@ogbrugge
Copy link
Contributor

Are you using the latest version of pcm?

@wangyi4
Copy link
Author

wangyi4 commented Apr 28, 2025

Yes, the latest version also has such issue.

@rdementi rdementi added the bug label May 6, 2025
@rdementi
Copy link
Contributor

rdementi commented May 6, 2025

we have a fix which should be merged soon

@rdementi
Copy link
Contributor

rdementi commented May 7, 2025

fixed in the master branch now

@wangyi4
Copy link
Author

wangyi4 commented May 8, 2025

I tried the latest master. It includes the fixings mentioned above. But the issue is still there.

@rdementi
Copy link
Contributor

rdementi commented May 8, 2025

@wangyi4 thank you for your feedback. Could you please share the current output from your system and the expected output from your point of view?

@wangyi4
Copy link
Author

wangyi4 commented May 8, 2025

The output is the same as what I reported before.
My understanding is that QAT should be connected to IDX instead of PCIe, like

|IIO Stack 0 - IDX0 |IB write|IB read|OB read|OB write|IOTLB Lookup|IOTLB Miss|Ctxt Cache Hit|256T Cache Hit|512G Cache Hit|1G Cache Hit|2M Cache Hit|IOMMU Mem Access|
||||||||||||||
| Part0 | 0 | 0 | 0 | 0 | 360 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Part1 | 0 | 0 | 0 | 0 |
| Part2 | 0 | 0 | 0 | 0 |
| Part3 | 0 | 0 | 0 | 0 |
| Part4 |7680 |3840 | 0 | 0 |
| Part5 | 0 | 0 | 0 | 0 |
| Part6 | 0 | 0 | 0 | 0 |
| Part7 | 0 | 0 | 0 | 0 |
|____________||
|
|||||||||______________|
|0000:6A:01.0|Gen0 x0 |8086:0B25 Intel Corporation unknown device; Part: 0, 1, 2
|0000:6B:00.0|Gen1 x1 |8086:4940 Intel Corporation 4xxx Series QAT; Part: 4
|0000:6D:00.0|Gen0 x0 |8086:2710 Intel Corporation unknown device; Part: 5

Correct me if my understanding is wrong.

On GNR-SP , I saw QAT was connected to HCx.


|IIO Stack 1 - HCx0 |IB write|IB read|OB read|OB write|IOTLB Lookup|IOTLB Miss|Ctxt Cache Hit|256T Cache Hit|512G Cache Hit|1G Cache Hit|2M Cache Hit|IOMMU Mem Access|
||________||||||||||||
| Part0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Part1 | 0 | 0 | 0 | 0 |
| Part2 | 0 | 0 | 0 | 0 |
| Part3 | 0 | 0 | 0 | 0 |
| Part4 | 0 | 0 | 0 | 0 |
| Part5 | 0 | 0 | 0 | 0 |
| Part6 | 0 | 0 | 0 | 0 |
| Part7 | 0 | 0 | 0 | 0 |
|
|________|||||||||||______________|
|0000:00:01.0|Gen0 x0 |8086:0B25 Intel Corporation unknown device; Part: 0
|0000:01:00.0|Gen1 x1 |8086:4944 Intel Corporation 4xxx Series QAT; Part: 4
|0000:03:00.0|Gen0 x0 |8086:2714 Intel Corporation unknown device; Part: 5

@antonovalexnn
Copy link
Contributor

Hi @wangyi4,
You are right. PCIe device mapping on stack ID for your platform is incorrect. I will contact you directly

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

No branches or pull requests

4 participants