Skip to content

Commit 54c8b5e

Browse files
reitermarkusreitermarkus
committed
Refactor rules.
1 parent c788e56 commit 54c8b5e

File tree

3 files changed

+251
-145
lines changed

3 files changed

+251
-145
lines changed

‎JLCPCB/JLCPCB.kicad_dru‎

Lines changed: 150 additions & 71 deletions
Original file line numberDiff line numberDiff line change
@@ -19,115 +19,194 @@
1919
# TODO new rule: non-plated slots: min diameter/width 1.0mm
2020
# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
2121

22-
(rule "Track width, outer layer (1oz copper)"
23-
(layer outer)
24-
(condition "A.Type == 'track'")
25-
(constraint track_width (min 0.127mm))
22+
23+
# --- Drill/Hole Size ---
24+
25+
(rule "Drill Hole Size"
26+
# Choose between:
27+
# 1-2 Layers
28+
# (constraint hole_size (min 0.3mm) (max 6.3mm))
29+
# 4-6 Layers (more costly)
30+
# (constraint hole_size (min 0.15mm) (max 6.3mm))
31+
# 4-6 Layers (preferred)
32+
(constraint hole_size (min 0.2mm) (max 6.3mm))
2633
)
2734

28-
(rule "Track spacing, outer layer (1oz copper)"
29-
(layer outer)
30-
(condition "A.Type == 'track' && B.Type == A.Type")
31-
(constraint clearance (min 0.127mm))
35+
(rule "Via Hole Size"
36+
(condition "A.Type == 'Via'")
37+
# Choose between:
38+
# 1-2 Layers
39+
# (constraint hole_size (min 0.3mm))
40+
# 4-6 Layers (more costly)
41+
# (constraint hole_size (min 0.15mm))
42+
# 4-6 Layers (preferred)
43+
(constraint hole_size (min 0.2mm))
3244
)
3345

34-
(rule "Track width, inner layer"
35-
(layer inner)
36-
(condition "A.Type == 'track'")
37-
(constraint track_width (min 0.09mm))
46+
(rule "Via Annular Ring"
47+
(condition "A.Type == 'Via'")
48+
# Choose between:
49+
# 1-6 Layers
50+
# (constraint annular_width (min 0.05mm))
51+
# 1-6 Layers (preferred)
52+
(constraint annular_width (min 0.075mm))
3853
)
3954

40-
(rule "Track spacing, inner layer"
41-
(layer inner)
42-
(condition "A.Type == 'track' && B.Type == A.Type")
43-
(constraint clearance (min 0.09mm))
55+
(rule "PTH Hole Size"
56+
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
57+
(constraint hole_size (min 0.2mm) (max 6.3mm))
4458
)
4559

46-
(rule "Silkscreen text"
47-
(layer "?.Silkscreen")
48-
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
49-
(constraint text_thickness (min 0.15mm))
50-
(constraint text_height (min 1mm))
60+
(rule "NPTH Hole Size"
61+
(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
62+
(constraint hole_size (min 0.5mm))
5163
)
5264

53-
(rule "Pad to Silkscreen"
65+
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm.
66+
(rule "Castellated Hole Size"
5467
(layer outer)
55-
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
56-
(constraint silk_clearance (min 0.15mm))
68+
(condition "A.Type == 'Pad' && A.Fabrication_Property == 'Castellated pad'")
69+
(constraint hole (min 0.6mm))
5770
)
5871

59-
(rule "Edge (routed) to track clearance"
60-
(condition "A.Type == 'track'")
61-
(constraint edge_clearance (min 0.3mm))
72+
(rule "PTH Annular Ring"
73+
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated()")
74+
(constraint annular_width (min 0.075mm))
6275
)
6376

64-
#(rule "Edge (v-cut) to track clearance"
65-
# (condition "A.Type == 'track'")
66-
# (constraint edge_clearance (min 0.4mm))
67-
#)
68-
69-
# JLCPCB restrictions ambiguous:
70-
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
71-
# This rule handles diameter minimum and maximum for ALL holes.
72-
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
73-
(rule "Hole diameter"
74-
(constraint hole_size (min 0.2mm) (max 6.3mm))
77+
(rule "NPTH Annular Ring"
78+
(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated()")
79+
(constraint annular_width (min 0.25mm))
7580
)
7681

77-
(rule "Hole (NPTH) diameter"
78-
(layer outer)
79-
(condition "!A.isPlated()")
80-
(constraint hole_size (min 0.5mm))
82+
83+
# --- Minimum Clearance ---
84+
85+
(rule "Hole to Hole Clearance (Different Nets)"
86+
(condition "A.Net != B.Net")
87+
(constraint hole_to_hole (min 0.5mm))
8188
)
8289

83-
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
84-
(rule "Hole (castellated) diameter"
85-
(layer outer)
86-
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
87-
(constraint hole_size (min 0.6mm))
90+
(rule "Via Hole to Via Hole Clearance (Same Net)"
91+
(condition "A.Type == 'Via' && B.Type == 'Via' && A.Net == B.Net")
92+
(constraint hole_to_hole (min 0.254mm))
8893
)
8994

90-
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
91-
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
92-
(rule "Annular ring width (via and PTH)"
93-
(layer outer)
94-
(condition "A.isPlated()")
95-
(constraint annular_width (min 0.075mm))
95+
(rule "Pad to Pad Clearance (Pad without Hole, Different Nets)"
96+
(condition "A.Type == 'Pad' && (A.Pad_Type != 'Through-hole' && A.Pad_Type != 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type != 'Through-hole' && B.Pad_Type != 'NPTH, mechanical') && && A.Net != B.Net")
97+
(constraint clearance (min 0.127mm))
9698
)
9799

98-
(rule "Clearance: hole to hole (perimeter), different nets"
99-
(layer outer)
100-
(condition "A.Net != B.Net")
100+
(rule "Pad Hole to Pad Hole Clearance (Pad with Hole, Different Nets)"
101+
(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Pad' && (B.Pad_Type == 'Through-hole' || B.Pad_Type == 'NPTH, mechanical') && && A.Net != B.Net")
101102
(constraint hole_to_hole (min 0.5mm))
102103
)
103104

104-
(rule "Clearance: hole to hole (perimeter), same net"
105-
(layer outer)
106-
(condition "A.Net == B.Net")
105+
# NOTE: This is not stated specifically, but is implied by other rules.
106+
(rule "Via/Pad to Via/Pad Clearance (Different Nets)"
107+
(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
108+
(constraint clearance (min 0.127mm))
109+
)
110+
111+
# NOTE: This is not stated specifically, but is implied by other rules.
112+
(rule "Via/Pad Hole to Via/Pad Hole Clearance (Same Net)"
113+
(condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net == B.Net")
107114
(constraint hole_to_hole (min 0.254mm))
108115
)
109116

110-
(rule "Clearance: track to NPTH hole (perimeter)"
111-
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
112-
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
117+
(rule "Via to Trace"
118+
(condition "A.Type == 'Via' && B.Type == 'Track'")
113119
(constraint hole_clearance (min 0.254mm))
114120
)
115121

116-
(rule "Clearance: track to PTH hole perimeter"
117-
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
122+
(rule "PTH to Trace"
123+
(condition "A.Type == 'Pad' && A.Pad_Type == 'Through-hole' && A.isPlated() && B.Type == 'Track'")
118124
(constraint hole_clearance (min 0.33mm))
119125
)
120126

121-
# TODO: try combining with rule "Clearance: PTH to track, different nets"
122-
(rule "Clearance: track to pad"
123-
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
127+
(rule "NPTH to Trace"
128+
(condition "A.Type == 'Pad' && A.Pad_Type == 'NPTH, mechanical' && !A.isPlated() && B.Type == 'Track'")
129+
(constraint hole_clearance (min 0.254mm))
130+
)
131+
132+
(rule "Pad to Trace"
133+
(condition "A.Type == 'Pad' && (A.Pad_Type == 'Through-hole' || A.Pad_Type == 'NPTH, mechanical') && B.Type == 'Track' && A.Net != B.Net")
124134
(constraint clearance (min 0.2mm))
125135
)
126136

127-
(rule "Clearance: pad/via to pad/via"
137+
138+
# --- Minimum Trace Width and Spacing ---
139+
140+
(rule "Trace Width (Outer Layer)"
128141
(layer outer)
129-
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
130-
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
131-
(constraint clearance (min 0.127mm))
142+
(condition "A.Type == 'Track'")
143+
# Choose between:
144+
# 1-2 Layers (1oz)
145+
# (constraint track_width (min 0.127mm))
146+
# 4-6 Layers (1oz and 0.5oz)
147+
(constraint track_width (min 0.09mm))
148+
# 1-6 Layers (2oz)
149+
# (constraint track_width (min 0.2mm))
150+
)
151+
(rule "Trace Spacing (Outer Layer)"
152+
(layer outer)
153+
(condition "A.Type == 'Track' && B.Type == 'Track'")
154+
# Choose between:
155+
# 1-2 Layers (1oz)
156+
# (constraint clearance (min 0.127mm))
157+
# 4-6 Layers (1oz and 0.5oz)
158+
(constraint clearance (min 0.09mm))
159+
# 1-6 Layers (2oz)
160+
# (constraint clearance (min 0.2mm))
161+
)
162+
163+
(rule "Trace Width (Inner Layer)"
164+
(layer inner)
165+
(condition "A.Type == 'Track'")
166+
# Choose between:
167+
# 4-6 Layers (1oz and 0.5oz)
168+
(constraint track_width (min 0.09mm))
169+
# 4-6 Layers (2oz)
170+
# (constraint track_width (min 0.2mm))
171+
)
172+
(rule "Trace Spacing (Inner Layer)"
173+
(layer inner)
174+
(condition "A.Type == 'Track' && B.Type == 'Track'")
175+
# Choose between:
176+
# 4-6 Layers (1oz and 0.5oz)
177+
(constraint clearance (min 0.09mm))
178+
# 4-6 Layers (2oz)
179+
# (constraint clearance (min 0.2mm))
180+
)
181+
182+
183+
# --- Legend ---
184+
185+
(rule "Minimum Line Width"
186+
(layer "?.Silkscreen")
187+
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
188+
(constraint text_thickness (min 0.15mm))
132189
)
133190

191+
(rule "Minimum Text Height"
192+
(layer "?.Silkscreen")
193+
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
194+
(constraint text_height (min 1mm))
195+
)
196+
197+
(rule "Pad to Silkscreen"
198+
(condition "A.Type == 'Pad' && ((A.existsOnLayer('F.Mask') && B.Layer == 'F.Silkscreen') || (A.existsOnLayer('B.Mask') && B.Layer == 'B.Silkscreen')) ")
199+
(constraint silk_clearance (min 0.15mm))
200+
)
201+
202+
203+
# --- Board Outlines ---
204+
205+
(rule "Trace to Board Edge"
206+
(condition "A.Type == 'Track'")
207+
# Choose between:
208+
# Routed
209+
(constraint edge_clearance (min 0.3mm))
210+
# V-Cut Panel
211+
# (constraint edge_clearance (min 0.4mm))
212+
)

0 commit comments

Comments
 (0)