diff --git a/JLCPCB/JLCPCB.kicad_dru b/JLCPCB/JLCPCB.kicad_dru
index c42eb3c..7e898bc 100644
--- a/JLCPCB/JLCPCB.kicad_dru
+++ b/JLCPCB/JLCPCB.kicad_dru
@@ -114,10 +114,15 @@
 )
 
 (rule "Clearance: track to PTH hole perimeter"
-	(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
+	(condition "A.isPlated() && A.Type != 'via' && B.Type == 'track' && A.Net != B.Net")
 	(constraint hole_clearance (min 0.33mm))
 )
 
+(rule "Clearance: track to Via hole perimeter"
+	(condition "A.Type == 'via' && B.Type == 'track' && A.Net != B.Net")
+	(constraint hole_clearance (min 0.254mm))
+)
+
 # TODO: try combining with rule "Clearance: PTH to track, different nets"
 (rule "Clearance: track to pad"
 	(condition "A.Type == 'pad' && B.Type == 'track' &&  A.Net != B.Net")