Skip to content

Commit 0239fb3

Browse files
lei137lei137
committed
add support and test for v2i64
1 parent a8a1c22 commit 0239fb3

File tree

2 files changed

+103
-52
lines changed

2 files changed

+103
-52
lines changed

‎llvm/lib/Target/PowerPC/PPCInstrFuture.td

Lines changed: 33 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -53,51 +53,52 @@ let Predicates = [IsISAFuture] in {
5353

5454
let Predicates = [HasVSX, IsISAFuture] in {
5555
let mayLoad = 1 in {
56-
def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
57-
"lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
58-
59-
def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
60-
"lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
61-
62-
def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
63-
(ins memr:$RA, g8rc:$RB),
64-
"lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
65-
66-
def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
67-
(ins memr:$RA, g8rc:$RB),
68-
"lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
56+
def LXVRL
57+
: XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
58+
"lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
59+
def LXVRLL
60+
: XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
61+
"lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
62+
def LXVPRL
63+
: XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp), (ins memr:$RA, g8rc:$RB),
64+
"lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
65+
def LXVPRLL
66+
: XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp), (ins memr:$RA, g8rc:$RB),
67+
"lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
6968
}
7069

7170
let mayStore = 1 in {
72-
def STXVRL : XX1Form_memOp<31, 653, (outs),
73-
(ins vsrc:$XT, memr:$RA, g8rc:$RB),
74-
"stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
75-
76-
def STXVRLL : XX1Form_memOp<31, 685, (outs),
77-
(ins vsrc:$XT, memr:$RA, g8rc:$RB),
78-
"stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
79-
71+
def STXVRL
72+
: XX1Form_memOp<31, 653, (outs), (ins vsrc:$XT, memr:$RA, g8rc:$RB),
73+
"stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
74+
def STXVRLL
75+
: XX1Form_memOp<31, 685, (outs), (ins vsrc:$XT, memr:$RA, g8rc:$RB),
76+
"stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
8077
def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
8178
(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
8279
"stxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
83-
8480
def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs),
8581
(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
8682
"stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
8783
}
8884
}
8985

90-
// Load VSX Vector with Right Length Left-justified.
91-
def : Pat<(v4i32 (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)), (LXVRL $RA, $RB)>;
92-
def : Pat<(v4i32 (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)), (LXVRLL $RA, $RB)>;
93-
def : Pat<(v256i1 (int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
94-
def : Pat<(v256i1 (int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
86+
// Load/Store VSX Vector with Right Length Left-justified.
87+
// foreach Ty = [v4i32, v2i64, v128i1] in {
88+
foreach Ty = [v4i32, v2i64] in {
89+
def : Pat<(Ty (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)),
90+
(LXVRL memr:$RA, g8rc:$RB)>;
91+
def : Pat<(Ty (int_ppc_vsx_lxvrll addr:$RA, i64:$RB)),
92+
(LXVRLL $RA, $RB)>;
93+
def : Pat<(int_ppc_vsx_stxvrl Ty:$XT, addr:$RA, i64:$RB),
94+
(STXVRL $XT, $RA, $RB)>;
95+
def : Pat<(int_ppc_vsx_stxvrll Ty:$XT, addr:$RA, i64:$RB),
96+
(STXVRLL $XT, $RA, $RB)>;
97+
}
9598

96-
// Store VSX Vector with Right Length Left-justified.
97-
def : Pat<(int_ppc_vsx_stxvrl v4i32:$XT, addr:$RA, i64:$RB),
98-
(STXVRL $XT, $RA, $RB)>;
99-
def : Pat<(int_ppc_vsx_stxvrll v4i32:$XT, addr:$RA, i64:$RB),
100-
(STXVRLL $XT, $RA, $RB)>;
99+
// Load/Store VSX Vector pair with Right Length Left-justified.
100+
def : Pat<(v256i1(int_ppc_vsx_lxvprl addr:$RA, i64:$RB)), (LXVPRL $RA, $RB)>;
101+
def : Pat<(v256i1(int_ppc_vsx_lxvprll addr:$RA, i64:$RB)), (LXVPRLL $RA, $RB)>;
101102
def : Pat<(int_ppc_vsx_stxvprl v256i1:$XTp, addr:$RA, i64:$RB),
102103
(STXVPRL $XTp, $RA, $RB)>;
103104
def : Pat<(int_ppc_vsx_stxvprll v256i1:$XTp, addr:$RA, i64:$RB),

‎llvm/test/CodeGen/PowerPC/vsx-ldst-with-length.ll

Lines changed: 70 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,8 @@
55
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=future < %s | \
66
; RUN: FileCheck %s
77

8+
; Test for load/store to/from v4i32.
9+
810
define <4 x i32> @testLXVRL(ptr %a, i64 %b) {
911
; CHECK-LABEL: testLXVRL:
1012
; CHECK: # %bb.0: # %entry
@@ -27,49 +29,97 @@ entry:
2729
}
2830
declare <4 x i32> @llvm.ppc.vsx.lxvrll(ptr, i64)
2931

30-
define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
31-
; CHECK-LABEL: testLXVPRL:
32+
define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
33+
; CHECK-LABEL: testSTXVRL:
3234
; CHECK: # %bb.0: # %entry
33-
; CHECK-NEXT: lxvprl vsp34, r4, r5
35+
; CHECK-NEXT: stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
3436
; CHECK: blr
3537
entry:
36-
%0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
37-
ret <256 x i1> %0
38+
tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
39+
ret void
3840
}
39-
declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
41+
declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
4042

41-
define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
42-
; CHECK-LABEL: testLXVPRLL:
43+
define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
44+
; CHECK-LABEL: testSTXVRLL:
4345
; CHECK: # %bb.0: # %entry
44-
; CHECK-NEXT: lxvprll vsp34, r4, r5
46+
; CHECK-NEXT: stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
4547
; CHECK: blr
4648
entry:
47-
%0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
48-
ret <256 x i1> %0
49+
tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
50+
ret void
4951
}
50-
declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
52+
declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
5153

52-
define void @testSTXVRL(<4 x i32> %a, ptr %b, i64 %c) {
53-
; CHECK-LABEL: testSTXVRL:
54+
; Test for load/store to/from v2i64.
55+
56+
define <2 x i64> @testLXVRL2(ptr %a, i64 %b) {
57+
; CHECK-LABEL: testLXVRL2:
58+
; CHECK: # %bb.0: # %entry
59+
; CHECK-NEXT: lxvrl v2, r3, r4
60+
; CHECK-NEXT: blr
61+
entry:
62+
%0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr %a, i64 %b)
63+
ret <2 x i64> %0
64+
}
65+
declare <2 x i64> @llvm.ppc.vsx.lxvrl.v2i64(ptr, i64)
66+
67+
define <2 x i64> @testLXVRLL2(ptr %a, i64 %b) {
68+
; CHECK-LABEL: testLXVRLL2:
69+
; CHECK: # %bb.0: # %entry
70+
; CHECK-NEXT: lxvrll v2, r3, r4
71+
; CHECK-NEXT: blr
72+
entry:
73+
%0 = tail call <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr %a, i64 %b)
74+
ret <2 x i64> %0
75+
}
76+
declare <2 x i64> @llvm.ppc.vsx.lxvrll.v2i64(ptr, i64)
77+
78+
define void @testSTXVRL2(<2 x i64> %a, ptr %b, i64 %c) {
79+
; CHECK-LABEL: testSTXVRL2:
5480
; CHECK: # %bb.0: # %entry
5581
; CHECK-NEXT: stxvrl v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
5682
; CHECK: blr
5783
entry:
58-
tail call void @llvm.ppc.vsx.stxvrl(<4 x i32> %a, ptr %b, i64 %c)
84+
tail call void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64> %a, ptr %b, i64 %c)
5985
ret void
6086
}
61-
declare void @llvm.ppc.vsx.stxvrl(<4 x i32>, ptr, i64)
87+
declare void @llvm.ppc.vsx.stxvrl.v2i64(<2 x i64>, ptr, i64)
6288

63-
define void @testSTXVRLL(<4 x i32> %a, ptr %b, i64 %c) {
64-
; CHECK-LABEL: testSTXVRLL:
89+
define void @testSTXVRLL2(<2 x i64> %a, ptr %b, i64 %c) {
90+
; CHECK-LABEL: testSTXVRLL2:
6591
; CHECK: # %bb.0: # %entry
6692
; CHECK-NEXT: stxvrll v2, [[REG:r[0-9]+]], [[REG1:r[0-9]+]]
6793
; CHECK: blr
6894
entry:
69-
tail call void @llvm.ppc.vsx.stxvrll(<4 x i32> %a, ptr %b, i64 %c)
95+
tail call void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64> %a, ptr %b, i64 %c)
7096
ret void
7197
}
72-
declare void @llvm.ppc.vsx.stxvrll(<4 x i32>, ptr, i64)
98+
declare void @llvm.ppc.vsx.stxvrll.v2i64(<2 x i64>, ptr, i64)
99+
100+
; Test for load/store vectore pair.
101+
102+
define <256 x i1> @testLXVPRL(ptr %vpp, i64 %b) {
103+
; CHECK-LABEL: testLXVPRL:
104+
; CHECK: # %bb.0: # %entry
105+
; CHECK-NEXT: lxvprl vsp34, r4, r5
106+
; CHECK: blr
107+
entry:
108+
%0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprl(ptr %vpp, i64 %b)
109+
ret <256 x i1> %0
110+
}
111+
declare <256 x i1> @llvm.ppc.vsx.lxvprl(ptr, i64)
112+
113+
define <256 x i1> @testLXVPRLL(ptr %vpp, i64 %b) {
114+
; CHECK-LABEL: testLXVPRLL:
115+
; CHECK: # %bb.0: # %entry
116+
; CHECK-NEXT: lxvprll vsp34, r4, r5
117+
; CHECK: blr
118+
entry:
119+
%0 = tail call <256 x i1> @llvm.ppc.vsx.lxvprll(ptr %vpp, i64 %b)
120+
ret <256 x i1> %0
121+
}
122+
declare <256 x i1> @llvm.ppc.vsx.lxvprll(ptr, i64)
73123

74124
define void @testSTXVPRL(ptr %v, ptr %vp, i64 %len) {
75125
; CHECK-LABEL: testSTXVPRL:

0 commit comments

Comments
 (0)