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Add test
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‎llvm/test/CodeGen/AMDGPU/avgpr-pressure.mir

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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -run-pass=machine-scheduler --debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
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# REQUIRES: asserts
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--- |
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define void @avgpr_rp_occ1() #0 {
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entry:
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unreachable
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}
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define void @avgpr_rp_occ2() #1 {
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entry:
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unreachable
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}
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define void @avgpr_rp_occ3() #2 {
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entry:
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unreachable
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}
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define void @avgpr_rp_occ4() #3 {
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entry:
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unreachable
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}
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define void @avgpr_rp_occ5() #4 {
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entry:
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unreachable
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}
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define void @avgpr_rp_occ6() #5 {
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entry:
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unreachable
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}
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define void @avgpr_rp_occ7() #6 {
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entry:
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unreachable
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}
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define void @avgpr_rp_occ8() #7 {
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entry:
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unreachable
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}
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attributes #0 = {"amdgpu-waves-per-eu"="1,1" "amdgpu-flat-work-group-size"="64,64"}
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attributes #1 = {"amdgpu-waves-per-eu"="2,2" "amdgpu-flat-work-group-size"="64,64"}
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attributes #2 = {"amdgpu-waves-per-eu"="3,3" "amdgpu-flat-work-group-size"="64,64"}
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attributes #3 = {"amdgpu-waves-per-eu"="4,4" "amdgpu-flat-work-group-size"="64,64"}
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attributes #4 = {"amdgpu-waves-per-eu"="5,5" "amdgpu-flat-work-group-size"="64,64"}
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attributes #5 = {"amdgpu-waves-per-eu"="6,6" "amdgpu-flat-work-group-size"="64,64"}
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attributes #6 = {"amdgpu-waves-per-eu"="7,7" "amdgpu-flat-work-group-size"="64,64"}
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attributes #7 = {"amdgpu-waves-per-eu"="8,8" "amdgpu-flat-work-group-size"="64,64"}
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...
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# CHECK: avgpr_rp_occ1:%bb.0
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# CHECK: Pressure before scheduling:
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# CHECK-NEXT: Region live-ins:
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# CHECK-NEXT: Region live-in pressure: VGPRs: 0 AGPRs: 0(O8), SGPRs: 0(O10), LVGPR WT: 0, LSGPR WT: 0 -> Occ: 8
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# CHECK-NEXT: Region register pressure: VGPRs: 256 AGPRs: 192(O1), SGPRs: 0(O10), LVGPR WT: 256, LSGPR WT: 0 -> Occ: 1
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---
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name: avgpr_rp_occ1
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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workGroupIDX: { reg: '$sgpr6' }
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privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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workItemIDX: { reg: '$vgpr0' }
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sgprForEXECCopy: '$sgpr100_sgpr101'
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr4_sgpr5
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%1:vreg_1024 = IMPLICIT_DEF
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%2:vreg_1024 = IMPLICIT_DEF
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%3:vreg_1024 = IMPLICIT_DEF
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%4:vreg_1024 = IMPLICIT_DEF
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%5:vreg_1024 = IMPLICIT_DEF
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%6:vreg_1024 = IMPLICIT_DEF
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%7:vreg_1024 = IMPLICIT_DEF
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%8:av_1024 = IMPLICIT_DEF
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%9:av_1024 = IMPLICIT_DEF
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%10:av_1024 = IMPLICIT_DEF
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%11:av_1024 = IMPLICIT_DEF
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%12:av_1024 = IMPLICIT_DEF
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%13:av_1024 = IMPLICIT_DEF
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%14:av_1024 = IMPLICIT_DEF
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SCHED_BARRIER 0
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KILL %1, %2, %3, %4, %5, %6, %7
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bb.1:
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KILL %8, %9, %10, %11, %12, %13, %14
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S_ENDPGM 0
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...
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# CHECK: avgpr_rp_occ2:%bb.0
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# CHECK: Pressure before scheduling:
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# CHECK-NEXT: Region live-ins:
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# CHECK-NEXT: Region live-in pressure: VGPRs: 0 AGPRs: 0(O8), SGPRs: 0(O10), LVGPR WT: 0, LSGPR WT: 0 -> Occ: 8
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# CHECK-NEXT: Region register pressure: VGPRs: 128 AGPRs: 64(O2), SGPRs: 0(O10), LVGPR WT: 128, LSGPR WT: 0 -> Occ: 2
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---
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name: avgpr_rp_occ2
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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workGroupIDX: { reg: '$sgpr6' }
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privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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workItemIDX: { reg: '$vgpr0' }
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sgprForEXECCopy: '$sgpr100_sgpr101'
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr4_sgpr5
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%1:vreg_1024 = IMPLICIT_DEF
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%2:vreg_1024 = IMPLICIT_DEF
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%3:vreg_1024 = IMPLICIT_DEF
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%4:av_1024 = IMPLICIT_DEF
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%5:av_1024 = IMPLICIT_DEF
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%6:av_1024 = IMPLICIT_DEF
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SCHED_BARRIER 0
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KILL %1, %2, %3
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bb.1:
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KILL %4, %5, %6
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S_ENDPGM 0
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...
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# CHECK: avgpr_rp_occ3:%bb.0
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# CHECK: Pressure before scheduling:
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# CHECK-NEXT: Region live-ins:
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# CHECK-NEXT: Region live-in pressure: VGPRs: 0 AGPRs: 0(O8), SGPRs: 0(O10), LVGPR WT: 0, LSGPR WT: 0 -> Occ: 8
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# CHECK-NEXT: Region register pressure: VGPRs: 84 AGPRs: 44(O4), SGPRs: 0(O10), LVGPR WT: 84, LSGPR WT: 0 -> Occ: 4
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---
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name: avgpr_rp_occ3
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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workGroupIDX: { reg: '$sgpr6' }
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privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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workItemIDX: { reg: '$vgpr0' }
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sgprForEXECCopy: '$sgpr100_sgpr101'
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr4_sgpr5
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%1:vreg_1024 = IMPLICIT_DEF
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%2:vreg_1024 = IMPLICIT_DEF
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%3:av_1024 = IMPLICIT_DEF
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%4:av_1024 = IMPLICIT_DEF
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SCHED_BARRIER 0
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KILL %1, %2
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bb.1:
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KILL %3, %4
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S_ENDPGM 0
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...
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# CHECK: avgpr_rp_occ4:%bb.0
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# CHECK: Pressure before scheduling:
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# CHECK-NEXT: Region live-ins:
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# CHECK-NEXT: Region live-in pressure: VGPRs: 0 AGPRs: 0(O8), SGPRs: 0(O10), LVGPR WT: 0, LSGPR WT: 0 -> Occ: 8
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# CHECK-NEXT: Region register pressure: VGPRs: 64 AGPRs: 64(O4), SGPRs: 0(O10), LVGPR WT: 64, LSGPR WT: 0 -> Occ: 4
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---
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name: avgpr_rp_occ4
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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workGroupIDX: { reg: '$sgpr6' }
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privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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workItemIDX: { reg: '$vgpr0' }
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sgprForEXECCopy: '$sgpr100_sgpr101'
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr4_sgpr5
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%1:vreg_1024 = IMPLICIT_DEF
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%2:vreg_1024 = IMPLICIT_DEF
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%3:av_1024 = IMPLICIT_DEF
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%4:av_1024 = IMPLICIT_DEF
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SCHED_BARRIER 0
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KILL %1, %2
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bb.1:
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KILL %3, %4
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S_ENDPGM 0
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...
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# CHECK: avgpr_rp_occ5:%bb.0
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# CHECK: Pressure before scheduling:
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# CHECK-NEXT: Region live-ins:
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# CHECK-NEXT: Region live-in pressure: VGPRs: 0 AGPRs: 0(O8), SGPRs: 0(O10), LVGPR WT: 0, LSGPR WT: 0 -> Occ: 8
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# CHECK-NEXT: Region register pressure: VGPRs: 48 AGPRs: 80(O4), SGPRs: 0(O10), LVGPR WT: 64, LSGPR WT: 0 -> Occ: 4
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---
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name: avgpr_rp_occ5
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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workGroupIDX: { reg: '$sgpr6' }
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privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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workItemIDX: { reg: '$vgpr0' }
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sgprForEXECCopy: '$sgpr100_sgpr101'
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr4_sgpr5
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%1:vreg_1024 = IMPLICIT_DEF
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%2:vreg_1024 = IMPLICIT_DEF
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%3:av_1024 = IMPLICIT_DEF
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%4:av_1024 = IMPLICIT_DEF
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SCHED_BARRIER 0
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KILL %1, %2
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bb.1:
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KILL %3, %4
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S_ENDPGM 0
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...
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# CHECK: avgpr_rp_occ6:%bb.0
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# CHECK: Pressure before scheduling:
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# CHECK-NEXT: Region live-ins:
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# CHECK-NEXT: Region live-in pressure: VGPRs: 0 AGPRs: 0(O8), SGPRs: 0(O10), LVGPR WT: 0, LSGPR WT: 0 -> Occ: 8
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# CHECK-NEXT: Region register pressure: VGPRs: 40 AGPRs: 88(O4), SGPRs: 0(O10), LVGPR WT: 64, LSGPR WT: 0 -> Occ: 4
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---
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name: avgpr_rp_occ6
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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workGroupIDX: { reg: '$sgpr6' }
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privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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workItemIDX: { reg: '$vgpr0' }
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sgprForEXECCopy: '$sgpr100_sgpr101'
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr4_sgpr5
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%1:vreg_1024 = IMPLICIT_DEF
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%2:vreg_1024 = IMPLICIT_DEF
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%3:av_1024 = IMPLICIT_DEF
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%4:av_1024 = IMPLICIT_DEF
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SCHED_BARRIER 0
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KILL %1, %2
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bb.1:
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KILL %3, %4
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S_ENDPGM 0
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...
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# CHECK: avgpr_rp_occ7:%bb.0
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# CHECK: Pressure before scheduling:
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# CHECK-NEXT: Region live-ins:
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# CHECK-NEXT: Region live-in pressure: VGPRs: 0 AGPRs: 0(O8), SGPRs: 0(O10), LVGPR WT: 0, LSGPR WT: 0 -> Occ: 8
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# CHECK-NEXT: Region register pressure: VGPRs: 36 AGPRs: 92(O4), SGPRs: 0(O10), LVGPR WT: 64, LSGPR WT: 0 -> Occ: 4
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---
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name: avgpr_rp_occ7
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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workGroupIDX: { reg: '$sgpr6' }
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privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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workItemIDX: { reg: '$vgpr0' }
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sgprForEXECCopy: '$sgpr100_sgpr101'
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr4_sgpr5
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%1:vreg_1024 = IMPLICIT_DEF
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%2:vreg_1024 = IMPLICIT_DEF
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%3:av_1024 = IMPLICIT_DEF
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%4:av_1024 = IMPLICIT_DEF
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SCHED_BARRIER 0
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KILL %1, %2
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bb.1:
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KILL %3, %4
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S_ENDPGM 0
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...
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# CHECK: avgpr_rp_occ8:%bb.0
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# CHECK: Pressure before scheduling:
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# CHECK-NEXT: Region live-ins:
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# CHECK-NEXT: Region live-in pressure: VGPRs: 0 AGPRs: 0(O8), SGPRs: 0(O10), LVGPR WT: 0, LSGPR WT: 0 -> Occ: 8
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# CHECK-NEXT: Region register pressure: VGPRs: 32 AGPRs: 96(O4), SGPRs: 0(O10), LVGPR WT: 64, LSGPR WT: 0 -> Occ: 4
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---
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name: avgpr_rp_occ8
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
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stackPtrOffsetReg: '$sgpr32'
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argumentInfo:
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privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
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kernargSegmentPtr: { reg: '$sgpr4_sgpr5' }
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workGroupIDX: { reg: '$sgpr6' }
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privateSegmentWaveByteOffset: { reg: '$sgpr7' }
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workItemIDX: { reg: '$vgpr0' }
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sgprForEXECCopy: '$sgpr100_sgpr101'
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr4_sgpr5
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%1:vreg_1024 = IMPLICIT_DEF
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%2:vreg_1024 = IMPLICIT_DEF
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%3:av_1024 = IMPLICIT_DEF
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%4:av_1024 = IMPLICIT_DEF
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SCHED_BARRIER 0
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KILL %1, %2
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bb.1:
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KILL %3, %4
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S_ENDPGM 0
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...
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