Search results

[DAG] visitFREEZE - limit freezing of multiple operands

backend:AMDGPU

backend:NVPTX

backend:PowerPC

backend:RISC-V

backend:SystemZ

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 150425

#150425 In llvm/llvm-project;

· RKSimon opened on Jul 24, 2025

[GISel] Introduce MachineIRBuilder::(build|materialize)ObjectPtrOffset

backend:AArch64

backend:AMDGPU

backend:ARM

backend:MIPS

backend:RISC-V

backend:X86

llvm:globalisel

Status: Open (in progress).

llvm/llvm-projectnumber 150392

#150392 In llvm/llvm-project;

· ritter-x2a opened on Jul 24, 2025

[VPlan] Remove VPBlendRecipe and replace with select VPInstructions

backend:RISC-V

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 150369

#150369 In llvm/llvm-project;

· lukel97 opened on Jul 24, 2025

[VPlan] Fold common edges away in convertPhisToBlends

backend:RISC-V

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 150368

#150368 In llvm/llvm-project;

· lukel97 opened on Jul 24, 2025

[RISCV] Implement load/store support for XAndesBFHCvt

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 150350

#150350 In llvm/llvm-project;

· tclin914 opened on Jul 24, 2025

RISC-V assembler should accept compressed shift hints with 0 immediates

backend:RISC-V

Status: Open.

#150304 In llvm/llvm-project;

· Timmmm opened on Jul 23, 2025

[IA] Recognize repeated masks which come from shuffle vectors

backend:RISC-V

llvm:codegen

Status: Open (in progress).

llvm/llvm-projectnumber 150285

#150285 In llvm/llvm-project;

· preames opened on Jul 23, 2025

[FMV][AArch64] Allow user to override version priority.

backend:AArch64

backend:ARM

backend:RISC-V

clangClang issues not falling into any other categoryClang issues not falling into any other category

clang:codegenIR generation bugs: mangling, exceptions, etc.IR generation bugs: mangling, exceptions, etc.

clang:frontendLanguage frontend issues, e.g. anything involving "Sema"Language frontend issues, e.g. anything involving "Sema"

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:transforms

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 150267

#150267 In llvm/llvm-project;

· labrinea opened on Jul 23, 2025

Improve handling of misaligned loads on RISC-V by introducing branching

backend:RISC-V

Status: Open.

#150263 In llvm/llvm-project;

· newpavlov opened on Jul 23, 2025

[RISCV] Pass sign-extended value to isInt check in expandMul

backend:RISC-V

Status: Open (in progress).

llvm/llvm-projectnumber 150211

#150211 In llvm/llvm-project;

· svs-quic opened on Jul 23, 2025

[VPlan] Fix header masks in EVL tail folding

backend:RISC-V

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 150202

#150202 In llvm/llvm-project;

· lukel97 opened on Jul 23, 2025

Unoptimized header masks mixed with VP intrinsics may have different lengths during EVL tail folding

backend:RISC-V

vectorizers

Status: Open.

#150197 In llvm/llvm-project;

· lukel97 opened on Jul 23, 2025