From a5a125c4ecc10902ab43f958eee81ce0ad3adf7c Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Wed, 23 Jul 2025 16:53:53 +0530 Subject: [PATCH 1/3] [RISCV] Pass sign-extended value to isInt check in expandMul In the isInt check that was added in # we were passing the zero-extended uint64_t value instead of the sign-extended one. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 3918dd21bc09d..fa0196ff25339 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -16079,7 +16079,7 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG, uint64_t MulAmt = CNode->getZExtValue(); // Don't do this if the Xqciac extension is enabled and the MulAmt in simm12. - if (Subtarget.hasVendorXqciac() && isInt<12>(MulAmt)) + if (Subtarget.hasVendorXqciac() && isInt<12>(CNode->getSExtValue())) return SDValue(); const bool HasShlAdd = Subtarget.hasStdExtZba() || From f64802066085e1bb54cd1838a95315a2290b3634 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Thu, 24 Jul 2025 18:47:00 +0530 Subject: [PATCH 2/3] Pre-commit test --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/test/CodeGen/RISCV/xqciac.ll | 24 +++++++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index fa0196ff25339..3918dd21bc09d 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -16079,7 +16079,7 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG, uint64_t MulAmt = CNode->getZExtValue(); // Don't do this if the Xqciac extension is enabled and the MulAmt in simm12. - if (Subtarget.hasVendorXqciac() && isInt<12>(CNode->getSExtValue())) + if (Subtarget.hasVendorXqciac() && isInt<12>(MulAmt)) return SDValue(); const bool HasShlAdd = Subtarget.hasStdExtZba() || diff --git a/llvm/test/CodeGen/RISCV/xqciac.ll b/llvm/test/CodeGen/RISCV/xqciac.ll index 4c77b391a47da..0ebca9324d3c8 100644 --- a/llvm/test/CodeGen/RISCV/xqciac.ll +++ b/llvm/test/CodeGen/RISCV/xqciac.ll @@ -463,3 +463,27 @@ entry: %add = add nsw i32 %shlc1, %shlc2 ret i32 %add } + +define i32 @testmuliaddnegimm(i32 %a, i32 %b) { +; RV32IM-LABEL: testmuliaddnegimm: +; RV32IM: # %bb.0: +; RV32IM-NEXT: slli a1, a0, 1 +; RV32IM-NEXT: add a0, a1, a0 +; RV32IM-NEXT: li a1, 3 +; RV32IM-NEXT: sub a0, a1, a0 +; RV32IM-NEXT: ret +; +; RV32IMXQCIAC-LABEL: testmuliaddnegimm: +; RV32IMXQCIAC: # %bb.0: +; RV32IMXQCIAC-NEXT: li a1, 3 +; RV32IMXQCIAC-NEXT: qc.muliadd a1, a0, -3 +; RV32IMXQCIAC-NEXT: mv a0, a1 +; RV32IMXQCIAC-NEXT: ret +; +; RV32IZBAMXQCIAC-LABEL: testmuliaddnegimm: +; RV32IZBAMXQCIAC: # %bb.0: +; RV32IZBAMXQCIAC-NEXT: ret + %mul = mul i32 %a, -3 + %add = add i32 %mul, 3 + ret i32 %add +} From 4b685d35796d90e5f99556d81f3075d31b9ba708 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Thu, 24 Jul 2025 18:51:38 +0530 Subject: [PATCH 3/3] Fix again --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/test/CodeGen/RISCV/xqciac.ll | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 3918dd21bc09d..fa0196ff25339 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -16079,7 +16079,7 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG, uint64_t MulAmt = CNode->getZExtValue(); // Don't do this if the Xqciac extension is enabled and the MulAmt in simm12. - if (Subtarget.hasVendorXqciac() && isInt<12>(MulAmt)) + if (Subtarget.hasVendorXqciac() && isInt<12>(CNode->getSExtValue())) return SDValue(); const bool HasShlAdd = Subtarget.hasStdExtZba() || diff --git a/llvm/test/CodeGen/RISCV/xqciac.ll b/llvm/test/CodeGen/RISCV/xqciac.ll index 0ebca9324d3c8..6fdc63fddbc30 100644 --- a/llvm/test/CodeGen/RISCV/xqciac.ll +++ b/llvm/test/CodeGen/RISCV/xqciac.ll @@ -464,7 +464,7 @@ entry: ret i32 %add } -define i32 @testmuliaddnegimm(i32 %a, i32 %b) { +define i32 @testmuliaddnegimm(i32 %a) { ; RV32IM-LABEL: testmuliaddnegimm: ; RV32IM: # %bb.0: ; RV32IM-NEXT: slli a1, a0, 1 @@ -482,6 +482,9 @@ define i32 @testmuliaddnegimm(i32 %a, i32 %b) { ; ; RV32IZBAMXQCIAC-LABEL: testmuliaddnegimm: ; RV32IZBAMXQCIAC: # %bb.0: +; RV32IZBAMXQCIAC-NEXT: li a1, 3 +; RV32IZBAMXQCIAC-NEXT: qc.muliadd a1, a0, -3 +; RV32IZBAMXQCIAC-NEXT: mv a0, a1 ; RV32IZBAMXQCIAC-NEXT: ret %mul = mul i32 %a, -3 %add = add i32 %mul, 3