From f9e2d2b0d76ed8297dc79002ec151b154a455a98 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 25 Jul 2025 17:52:11 +0000 Subject: [PATCH 1/8] Implement vector uncompress instructions --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 1ac91fadf6582..3167e3d21485a 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -45,6 +45,20 @@ multiclass XOForm_RTAB5_L1r opcode, bits<9> xo, dag OOL, dag IOL, } } +class VXForm_VRTAB5 xo, dag OOL, dag IOL, string asmstr, + list pattern> : I<4, OOL, IOL, asmstr, NoItinerary> { + bits<5> VRT; + bits<5> VRA; + bits<5> VRB; + + let Pattern = pattern; + + let Inst{6-10} = VRT; + let Inst{11-15} = VRA; + let Inst{16-20} = VRB; + let Inst{21-31} = xo; +} + let Predicates = [IsISAFuture] in { defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, u1imm:$L), @@ -85,4 +99,17 @@ let Predicates = [HasVSX, IsISAFuture] in { (ins vsrprc:$XTp, memr:$RA, g8rc:$RB), "stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>; } + + def VUCMPRHN : VXForm_VRTAB5<3, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprhn $VRT, $VRA, $VRB", []>; + def VUCMPRLN : VXForm_VRTAB5<67, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprln $VRT, $VRA, $VRB", []>; + def VUCMPRHB : VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprhb $VRT, $VRA, $VRB", []>; + def VUCMPRLB : VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprlb $VRT, $VRA, $VRB", []>; + def VUCMPRHH : VXForm_VRTAB5<295, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprhh $VRT, $VRA, $VRB", []>; + def VUCMPRLH : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprlh $VRT, $VRA, $VRB", []>; } From 95870ef4908791b9edd9648ca65f9738eb98f416 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 25 Jul 2025 20:23:55 +0000 Subject: [PATCH 2/8] add encoding tests --- .../Disassembler/PowerPC/ppc-encoding-ISAFuture.txt | 9 +++++++++ .../PowerPC/ppc64le-encoding-ISAFuture.txt | 9 +++++++++ llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 12 ++++++++++++ 3 files changed, 30 insertions(+) diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index 4bea42243f83b..80b4ba21de8ad 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -195,3 +195,12 @@ #CHECK: dmxxsha224256pad 0, 1 0xf0,0x18,0x0e,0x94 + +#CHECK: vucmprhn 0, 2, 3 +0x10,0x02,0x18,0x03 + +#CHECK: vucmprln 3, 5, 6 +0x10,0x65,0x30,0x43 + +#CHECK: vucmprhb 1, 3, 6 +0x10,0x23,0x30,0x83 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index 233693e67292e..220ae045f7066 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -189,3 +189,12 @@ #CHECK: dmxxsha224256pad 0, 1 0x94,0x0e,0x18,0xf0 + +#CHECK: vucmprhn 0, 2, 3 +0x03,0x18,0x02,0x10 + +#CHECK: vucmprln 3, 5, 6 +0x43,0x30,0x65,0x10 + +#CHECK: vucmprhb 1, 3, 6 +0x83,0x30,0x23,0x10 diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index cba93291e4595..a61133bca69ed 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -282,3 +282,15 @@ dmxxsha224256pad 0, 1 #CHECK-BE: dmxxsha224256pad 0, 1 # encoding: [0xf0,0x18,0x0e,0x94] #CHECK-LE: dmxxsha224256pad 0, 1 # encoding: [0x94,0x0e,0x18,0xf0] + + vucmprhn 0, 2, 3 +#CHECK-BE: vucmprhn 0, 2, 3 # encoding: [0x10,0x02,0x18,0x03] +#CHECK-LE: vucmprhn 0, 2, 3 # encoding: [0x03,0x18,0x02,0x10] + + vucmprln 3, 5, 6 +#CHECK-BE: vucmprln 3, 5, 6 # encoding: [0x10,0x65,0x30,0x43] +#CHECK-LE: vucmprln 3, 5, 6 # encoding: [0x43,0x30,0x65,0x10] + + vucmprhb 1, 3, 6 +#CHECK-BE: vucmprhb 1, 3, 6 # encoding: [0x10,0x23,0x30,0x83] +#CHECK-LE: vucmprhb 1, 3, 6 # encoding: [0x83,0x30,0x23,0x10] From 6a0dc8740ef0536b94489b4eb439cefde069c449 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 25 Jul 2025 20:31:26 +0000 Subject: [PATCH 3/8] add more encoding tests --- .../test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt | 3 +++ .../MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt | 3 +++ llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 6 +++++- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index 80b4ba21de8ad..c967c4b264aa3 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -204,3 +204,6 @@ #CHECK: vucmprhb 1, 3, 6 0x10,0x23,0x30,0x83 + +#CHECK: vucmprlb 2, 4, 5 +0x10,0x44,0x28,0xC3 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index 220ae045f7066..cedf90639a35d 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -198,3 +198,6 @@ #CHECK: vucmprhb 1, 3, 6 0x83,0x30,0x23,0x10 + +#CHECK: vucmprlb 2, 4, 5 +0xC3,0x28,0x44,0x10 diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index a61133bca69ed..6fc8f882ef06f 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -291,6 +291,10 @@ #CHECK-BE: vucmprln 3, 5, 6 # encoding: [0x10,0x65,0x30,0x43] #CHECK-LE: vucmprln 3, 5, 6 # encoding: [0x43,0x30,0x65,0x10] - vucmprhb 1, 3, 6 + vucmprhb 1, 3, 6 #CHECK-BE: vucmprhb 1, 3, 6 # encoding: [0x10,0x23,0x30,0x83] #CHECK-LE: vucmprhb 1, 3, 6 # encoding: [0x83,0x30,0x23,0x10] + + vucmprlb 2, 4, 5 +#CHECK-BE: vucmprlb 2, 4, 5 # encoding: [0x10,0x44,0x28,0xc3] +#CHECK-LE: vucmprlb 2, 4, 5 # encoding: [0xc3,0x28,0x44,0x10] From 8c921fbfc1ab7971ded4b7e9beb77f7d93907e8e Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 25 Jul 2025 20:49:46 +0000 Subject: [PATCH 4/8] add more encoding tests --- llvm/test/MC/Disassembler/PowerPC/lei.txt | 14 ++++++++++++++ .../PowerPC/ppc-encoding-ISAFuture.txt | 3 +++ .../PowerPC/ppc64le-encoding-ISAFuture.txt | 4 ++++ llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 4 ++++ 4 files changed, 25 insertions(+) create mode 100644 llvm/test/MC/Disassembler/PowerPC/lei.txt diff --git a/llvm/test/MC/Disassembler/PowerPC/lei.txt b/llvm/test/MC/Disassembler/PowerPC/lei.txt new file mode 100644 index 0000000000000..d778d73c86117 --- /dev/null +++ b/llvm/test/MC/Disassembler/PowerPC/lei.txt @@ -0,0 +1,14 @@ +# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \ +# RUN: -mcpu=future | FileCheck %s + +# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-aix-gnu \ +# RUN: -mcpu=future | FileCheck %s + +# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-aix-gnu \ +# RUN: -mcpu=future | FileCheck %s + +# vucmprhh 1, 3, 6 +# 0x10,0x23,0x31,0x03 + +#CHECK: vucmprlh 2, 4, 5 +0x10,0x44,0x29,0x43 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index c967c4b264aa3..7cb4a8d59510f 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -207,3 +207,6 @@ #CHECK: vucmprlb 2, 4, 5 0x10,0x44,0x28,0xC3 + +#CHECK: vucmprlh 2, 4, 5 +0x10,0x44,0x29,0x43 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index cedf90639a35d..90550e82796c8 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -201,3 +201,7 @@ #CHECK: vucmprlb 2, 4, 5 0xC3,0x28,0x44,0x10 + +#CHECK: vucmprlh 2, 4, 5 +0x43,0x29,0x44,0x10 + diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index 6fc8f882ef06f..bc3bbd2aeabce 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -298,3 +298,7 @@ vucmprlb 2, 4, 5 #CHECK-BE: vucmprlb 2, 4, 5 # encoding: [0x10,0x44,0x28,0xc3] #CHECK-LE: vucmprlb 2, 4, 5 # encoding: [0xc3,0x28,0x44,0x10] + + vucmprlh 2, 4, 5 +#CHECK-BE: vucmprlh 2, 4, 5 # encoding: [0x10,0x44,0x29,0x43] +#CHECK-LE: vucmprlh 2, 4, 5 # encoding: [0x43,0x29,0x44,0x10] From 5b5878677ca47666e97d799fc3ea9659c24ce1ff Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 25 Jul 2025 20:51:46 +0000 Subject: [PATCH 5/8] fix xo encoding for vucmprhh --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 3167e3d21485a..8cd98faeb9e92 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -108,7 +108,7 @@ let Predicates = [HasVSX, IsISAFuture] in { "vucmprhb $VRT, $VRA, $VRB", []>; def VUCMPRLB : VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), "vucmprlb $VRT, $VRA, $VRB", []>; - def VUCMPRHH : VXForm_VRTAB5<295, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + def VUCMPRHH : VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), "vucmprhh $VRT, $VRA, $VRB", []>; def VUCMPRLH : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), "vucmprlh $VRT, $VRA, $VRB", []>; From 3486f5076475ce740dac97226e42710f34e8fed3 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 25 Jul 2025 20:55:04 +0000 Subject: [PATCH 6/8] add last encoding test --- llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt | 3 +++ .../MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt | 2 ++ llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index 7cb4a8d59510f..e944771f8a298 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -210,3 +210,6 @@ #CHECK: vucmprlh 2, 4, 5 0x10,0x44,0x29,0x43 + +#CHECK: vucmprhh 1, 3, 6 +0x10,0x23,0x31,0x03 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index 90550e82796c8..e146d9ec32fc7 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -205,3 +205,5 @@ #CHECK: vucmprlh 2, 4, 5 0x43,0x29,0x44,0x10 +#CHECK: vucmprhh 1, 3, 6 +0x03,0x31,0x23,0x10 diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index bc3bbd2aeabce..f3b86ae8dff72 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -302,3 +302,7 @@ vucmprlh 2, 4, 5 #CHECK-BE: vucmprlh 2, 4, 5 # encoding: [0x10,0x44,0x29,0x43] #CHECK-LE: vucmprlh 2, 4, 5 # encoding: [0x43,0x29,0x44,0x10] + + vucmprhh 1, 3, 6 +#CHECK-BE: vucmprhh 1, 3, 6 # encoding: [0x10,0x23,0x31,0x03] +#CHECK-LE: vucmprhh 1, 3, 6 # encoding: [0x03,0x31,0x23,0x10] From 962ff0291735b0c92c6c5e1332e6f52c567d5dc2 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 25 Jul 2025 20:59:39 +0000 Subject: [PATCH 7/8] remove accidental new file --- llvm/test/MC/Disassembler/PowerPC/lei.txt | 14 -------------- 1 file changed, 14 deletions(-) delete mode 100644 llvm/test/MC/Disassembler/PowerPC/lei.txt diff --git a/llvm/test/MC/Disassembler/PowerPC/lei.txt b/llvm/test/MC/Disassembler/PowerPC/lei.txt deleted file mode 100644 index d778d73c86117..0000000000000 --- a/llvm/test/MC/Disassembler/PowerPC/lei.txt +++ /dev/null @@ -1,14 +0,0 @@ -# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \ -# RUN: -mcpu=future | FileCheck %s - -# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-aix-gnu \ -# RUN: -mcpu=future | FileCheck %s - -# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-aix-gnu \ -# RUN: -mcpu=future | FileCheck %s - -# vucmprhh 1, 3, 6 -# 0x10,0x23,0x31,0x03 - -#CHECK: vucmprlh 2, 4, 5 -0x10,0x44,0x29,0x43 From 49fe55fb1e0d23f5c2e339d3da02df6b10b4a321 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 25 Jul 2025 21:03:08 +0000 Subject: [PATCH 8/8] apply clang-format --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 28 +++++++++++++---------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 8cd98faeb9e92..0693b4537178f 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -53,10 +53,10 @@ class VXForm_VRTAB5 xo, dag OOL, dag IOL, string asmstr, let Pattern = pattern; - let Inst{6-10} = VRT; - let Inst{11-15} = VRA; - let Inst{16-20} = VRB; - let Inst{21-31} = xo; + let Inst{6 -10} = VRT; + let Inst{11 -15} = VRA; + let Inst{16 -20} = VRB; + let Inst{21 -31} = xo; } let Predicates = [IsISAFuture] in { @@ -104,12 +104,16 @@ let Predicates = [HasVSX, IsISAFuture] in { "vucmprhn $VRT, $VRA, $VRB", []>; def VUCMPRLN : VXForm_VRTAB5<67, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), "vucmprln $VRT, $VRA, $VRB", []>; - def VUCMPRHB : VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), - "vucmprhb $VRT, $VRA, $VRB", []>; - def VUCMPRLB : VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), - "vucmprlb $VRT, $VRA, $VRB", []>; - def VUCMPRHH : VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), - "vucmprhh $VRT, $VRA, $VRB", []>; - def VUCMPRLH : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), - "vucmprlh $VRT, $VRA, $VRB", []>; + def VUCMPRHB + : VXForm_VRTAB5<131, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprhb $VRT, $VRA, $VRB", []>; + def VUCMPRLB + : VXForm_VRTAB5<195, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprlb $VRT, $VRA, $VRB", []>; + def VUCMPRHH + : VXForm_VRTAB5<259, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprhh $VRT, $VRA, $VRB", []>; + def VUCMPRLH + : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), + "vucmprlh $VRT, $VRA, $VRB", []>; }