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enable verible-verilog-ls for verilog filetype
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README.md

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@@ -103,7 +103,7 @@ If you encounter any problems even if it's not related to this feature, **deleti
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| [svls](https://github.com/dalance/svls) | not supported | enabled | not supported |
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| [veridian](https://github.com/vivekmalneedi/veridian) | not supported | enabled | not supported |
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| [HDL Checker](https://github.com/suoto/hdl_checker) | enabled | enabled | enabled |
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| [verible-verilog-ls](https://github.com/chipsalliance/verible) | not supported | enabled | not supported |
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| [verible-verilog-ls](https://github.com/chipsalliance/verible) | enabled | enabled | not supported |
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| [rust_hdl](https://github.com/VHDL-LS/rust_hdl) | not supported | not supported | enabled |
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### Formatting (Experimental)

src/extension.ts

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@@ -243,7 +243,10 @@ function initAllLanguageClients() {
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// init verible-verilog-ls
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setupLanguageClient('veribleVerilogLs', 'verible-verilog-ls', [], [], {
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documentSelector: [{ scheme: 'file', language: 'systemverilog' }],
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documentSelector: [
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{ scheme: 'file', language: 'verilog' },
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{ scheme: 'file', language: 'systemverilog' },
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],
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});
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// init rustHdl

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