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perigosoperigoso
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platform/sam3u: add startup
Signed-off-by: perigoso <perigoso@riseup.net>
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‎src/platform/sam3u/startup.c

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/*
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* SPDX-License-Identifier: MIT
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* SPDX-FileCopyrightText: 2021 Rafael Silva <perigoso@riseup.net>
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*/
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#include <sam.h>
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#include "util/types.h"
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/* Stack pointer */
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extern void _estack(); /* Not a function, just to be compatible with the vector table array */
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/* Variables */
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extern u32 _svect; /* ISR Vectors */
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extern u32 _evect;
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extern u32 _stext; /* Main program */
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extern u32 _etext;
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extern u32 _sidata; /* Data source */
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extern u32 _sdata; /* Data destination */
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extern u32 _edata;
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extern u32 _sbss; /* BSS destination */
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extern u32 _ebss;
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extern u32 _end;
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/* Functions */
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void _default_isr()
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{
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while (1) continue;
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}
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void __attribute__((weak)) __libc_init_array()
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{
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}
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extern void __attribute__((noreturn)) main();
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#define DEFAULT_ISR "_default_isr"
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void _reset_isr()
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{
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u32 *src, *dst;
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src = &_sidata;
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dst = &_sdata;
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while (dst < &_edata) /* Copy data */
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*(dst++) = *(src++);
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src = 0;
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dst = &_sbss;
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while (dst < &_ebss) /* Zero BSS */
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*(dst++) = 0;
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__libc_init_array();
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SCB->VTOR = (u32) &_svect; /* ISR Vectors offset */
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SCB->AIRCR = 0x05FA0000 | (4 << 8); /* Interrupt priority - 3 bits Group, 1 bit Sub-group */
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SCB->SHCSR = SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk |
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SCB_SHCSR_MEMFAULTENA_Msk; /* Enable separate fault handlers */
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main();
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__disable_irq();
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while (1) continue;
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}
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/* Cortex-M Exception Handlers */
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void _nmi_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _hardfault_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _memmanage_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _busfault_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _usagefault_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _svc_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _debugmon_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _pendsv_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _systick_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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/* External interrupts */
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void _supc_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _rstc_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _rtc_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _rtt_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _wdt_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _pmc_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _efc0_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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#ifdef _SAM3U_EFC1_INSTANCE_
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void _efc1_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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#endif /* _SAM3U_EFC1_INSTANCE_ */
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void _uart_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _pioa_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _piob_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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#ifdef _SAM3U_PIOC_INSTANCE_
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void _pioc_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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#endif /* _SAM3U_PIOC_INSTANCE_ */
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void _usart0_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _usart1_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _usart2_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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#ifdef _SAM3U_USART3_INSTANCE_
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void _usart3_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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#endif /* _SAM3U_USART3_INSTANCE_ */
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void _hsmci_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _twi0_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _twi1_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _spi_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _ssc_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _tc0_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _tc1_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _tc2_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _pwm_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _adc12b_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _adc_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _dmac_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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void _udphs_isr() __attribute__((weak, alias(DEFAULT_ISR)));
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/* Vector table */
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__attribute__((section(".isr_vector"), used)) void (*const g_pfnVectors[])() = {
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/* Cortex-M Exception Handlers */
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_estack,
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_reset_isr,
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_nmi_isr,
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_hardfault_isr,
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_memmanage_isr,
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_busfault_isr,
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_usagefault_isr,
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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0, /* Reserved */
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_svc_isr,
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_debugmon_isr,
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0, /* Reserved */
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_pendsv_isr,
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_systick_isr,
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/* External interrupts */
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_supc_isr, /* 0 Supply Controller */
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_rstc_isr, /* 1 Reset Controller */
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_rtc_isr, /* 2 Real Time Clock */
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_rtt_isr, /* 3 Real Time Timer */
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_wdt_isr, /* 4 Watchdog Timer */
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_pmc_isr, /* 5 Power Management Controller */
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_efc0_isr, /* 6 Enhanced Embedded Flash Controller 0 */
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#ifdef _SAM3U_EFC1_INSTANCE_
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_efc1_isr, /* 7 Enhanced Embedded Flash Controller 1 */
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#else
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0, /* 7 Reserved */
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#endif /* _SAM3U_EFC1_INSTANCE_ */
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_uart_isr, /* 8 Universal Asynchronous Receiver Transmitter */
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0, /* 9 Reserved */
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_pioa_isr, /* 10 Parallel I/O Controller A, */
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_piob_isr, /* 11 Parallel I/O Controller B */
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#ifdef _SAM3U_PIOC_INSTANCE_
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_pioc_isr, /* 12 Parallel I/O Controller C */
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#else
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0, /* 12 Reserved */
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#endif /* _SAM3U_PIOC_INSTANCE_ */
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_usart0_isr, /* 13 USART 0 */
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_usart1_isr, /* 14 USART 1 */
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_usart2_isr, /* 15 USART 2 */
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#ifdef _SAM3U_USART3_INSTANCE_
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_usart3_isr, /* 16 USART 3 */
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#else
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0, /* 16 Reserved */
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#endif /* _SAM3U_USART3_INSTANCE_ */
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_hsmci_isr, /* 17 High Speed Multimedia Card Interface */
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_twi0_isr, /* 18 Two-Wire Interface 0 */
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_twi1_isr, /* 19 Two-Wire Interface 1 */
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_spi_isr, /* 20 Serial Peripheral Interface */
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_ssc_isr, /* 21 Synchronous Serial Controller */
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_tc0_isr, /* 22 Timer Counter 0 */
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_tc1_isr, /* 23 Timer Counter 1 */
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_tc2_isr, /* 24 Timer Counter 2 */
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_pwm_isr, /* 25 Pulse Width Modulation Controller */
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_adc12b_isr, /* 26 12-bit ADC Controller */
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_adc_isr, /* 27 10-bit ADC Controller */
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_dmac_isr, /* 28 DMA Controller */
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_udphs_isr, /* 29 USB Device High Speed */
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};

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