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perigosoperigoso
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platform/sam3u: initial pmc
Signed-off-by: Rafael Silva <perigoso@riseup.net>
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‎config/families/sam3u.toml‎

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@@ -31,6 +31,7 @@ source = [
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'startup.c',
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'eefc.c',
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'wdt.c',
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'pmc.c',
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]
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[dependencies]

‎src/platform/sam3u/pmc.c‎

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/*
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* SPDX-License-Identifier: MIT
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* SPDX-FileCopyrightText: 2021 Rafael Silva <perigoso@riseup.net>
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*/
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#include <sam.h>
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#include "util/data.h"
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#include "platform/sam3u/eefc.h"
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#include "platform/sam3u/pmc.h"
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static struct pmc_clock_tree_t pmc_clock_tree;
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void pmc_init(u32 hfxo_freq, u32 lfxo_freq)
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{
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if (hfxo_freq != 12000000UL) // this is a preset for 12MHz Crystal
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return;
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pmc_clock_tree.hfxo_freq = hfxo_freq;
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pmc_clock_tree.lfxo_freq = lfxo_freq;
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/* Configure flash waitstates */
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eefc_config_waitstates(96000000);
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/* 12MHz external xtal, maximum possible startup time */
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pmc_hfxo_enable(false, 0xFF);
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/* Select as main oscillator */
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pmc_mainck_source_set(PMC_MAINCK_HFXO);
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pmc_mck_source_set(PMC_MCK_MAINCK, 1);
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/* Multiply by 8 for 96MHz */
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pmc_pllack_enable(8, 1);
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pmc_upllck_enable();
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/* Select as MCK source */
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pmc_mck_source_set(PMC_MCK_PLLACK, 1);
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}
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void pmc_update_clock_tree()
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{
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pmc_clock_tree.lfrco_freq = CHIP_FREQ_SLCK_RC;
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switch (SUPC->SUPC_SR & SUPC_SR_OSCSEL) {
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case SUPC_SR_OSCSEL_RC:
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pmc_clock_tree.slck_freq = pmc_clock_tree.lfrco_freq;
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break;
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case SUPC_SR_OSCSEL_CRYST:
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pmc_clock_tree.slck_freq = pmc_clock_tree.lfxo_freq;
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break;
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}
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switch (PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk) {
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case CKGR_MOR_MOSCRCF_4_MHz:
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pmc_clock_tree.hfrco_freq = CHIP_FREQ_MAINCK_RC_4MHZ;
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break;
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case CKGR_MOR_MOSCRCF_8_MHz:
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pmc_clock_tree.hfrco_freq = CHIP_FREQ_MAINCK_RC_8MHZ;
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break;
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case CKGR_MOR_MOSCRCF_12_MHz:
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pmc_clock_tree.hfrco_freq = CHIP_FREQ_MAINCK_RC_12MHZ;
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break;
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}
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switch (PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) {
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case 0:
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pmc_clock_tree.mainck_freq = pmc_clock_tree.hfrco_freq;
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break;
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case CKGR_MOR_MOSCSEL:
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pmc_clock_tree.mainck_freq = pmc_clock_tree.hfxo_freq;
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break;
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}
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float plla_div = (PMC->CKGR_PLLAR & CKGR_PLLAR_DIVA_Msk) >> CKGR_PLLAR_DIVA_Pos;
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float plla_mul = (PMC->CKGR_PLLAR & CKGR_PLLAR_MULA_Msk) >> CKGR_PLLAR_MULA_Pos;
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if (plla_div == 0 || plla_mul == 0)
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pmc_clock_tree.pllack_freq = 0;
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else
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pmc_clock_tree.pllack_freq = (uint32_t) (((float) pmc_clock_tree.mainck_freq / plla_div) * (plla_mul + 1.f));
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if (!(PMC->CKGR_UCKR & CKGR_UCKR_UPLLEN))
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pmc_clock_tree.upllck_freq = 0;
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else
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pmc_clock_tree.upllck_freq = CHIP_FREQ_UTMIPLL;
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switch (PMC->PMC_MCKR & PMC_MCKR_CSS_Msk) {
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case PMC_MCKR_CSS_SLOW_CLK:
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pmc_clock_tree.mck_freq = pmc_clock_tree.slck_freq;
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break;
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case PMC_MCKR_CSS_MAIN_CLK:
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pmc_clock_tree.mck_freq = pmc_clock_tree.mainck_freq;
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break;
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case PMC_MCKR_CSS_UPLL_CLK:
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pmc_clock_tree.mck_freq = pmc_clock_tree.upllck_freq / 2;
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break;
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case PMC_MCKR_CSS_PLLA_CLK:
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pmc_clock_tree.mck_freq = pmc_clock_tree.pllack_freq;
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break;
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}
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switch (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) {
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case PMC_MCKR_PRES_CLK_1:
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pmc_clock_tree.mck_freq >>= 0;
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break;
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case PMC_MCKR_PRES_CLK_2:
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pmc_clock_tree.mck_freq >>= 1;
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break;
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case PMC_MCKR_PRES_CLK_4:
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pmc_clock_tree.mck_freq >>= 2;
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break;
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case PMC_MCKR_PRES_CLK_8:
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pmc_clock_tree.mck_freq >>= 3;
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break;
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case PMC_MCKR_PRES_CLK_16:
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pmc_clock_tree.mck_freq >>= 4;
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break;
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case PMC_MCKR_PRES_CLK_32:
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pmc_clock_tree.mck_freq >>= 5;
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break;
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case PMC_MCKR_PRES_CLK_64:
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pmc_clock_tree.mck_freq >>= 6;
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break;
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case PMC_MCKR_PRES_CLK_3:
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pmc_clock_tree.mck_freq /= 3;
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break;
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}
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pmc_clock_tree.fclk_freq = pmc_clock_tree.mck_freq;
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}
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const struct pmc_clock_tree_t *pmc_get_clock_tree()
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{
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return (const struct pmc_clock_tree_t *) &pmc_clock_tree;
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}
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void pmc_hfxo_enable(bool bypass, u8 startup_time)
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{
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if (bypass) {
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~(CKGR_MOR_MOSCXTEN)) | CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCXTBY;
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} else {
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~(CKGR_MOR_MOSCXTST_Msk | CKGR_MOR_MOSCXTBY)) | CKGR_MOR_KEY_PASSWD |
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CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCXTST(startup_time);
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}
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while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) continue;
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}
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void pmc_hfxo_disable()
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{
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~(CKGR_MOR_MOSCXTBY | CKGR_MOR_MOSCXTEN)) | CKGR_MOR_KEY_PASSWD;
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}
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void pmc_hfrco_enable(enum pmc_hfrco_freq_t freq)
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{
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PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN);
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) continue;
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCF(freq);
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) continue;
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}
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void pmc_hfrco_disable()
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{
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~(CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCRCF_Msk)) | CKGR_MOR_KEY_PASSWD;
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}
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void pmc_pllack_enable(u8 mul, u8 div)
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{
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pmc_pllack_disable();
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if (!mul || !div)
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mul = div = 1;
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PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(mul - 1) | CKGR_PLLAR_DIVA(div) | CKGR_PLLAR_PLLACOUNT(63);
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while (!(PMC->PMC_SR & PMC_SR_LOCKA)) continue;
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}
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void pmc_pllack_disable()
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{
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PMC->CKGR_PLLAR = CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0) | CKGR_PLLAR_DIVA(0);
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}
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void pmc_upllck_enable()
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{
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pmc_upllck_disable();
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PMC->CKGR_UCKR = CKGR_UCKR_UPLLCOUNT(255) | CKGR_UCKR_UPLLEN;
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while (!(PMC->PMC_SR & PMC_SR_LOCKU)) continue;
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}
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void pmc_upllck_disable()
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{
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PMC->CKGR_UCKR &= ~CKGR_UCKR_UPLLEN;
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}
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void pmc_slck_source_set(enum pmc_slck_src_t src)
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{
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if (src == PMC_SCLK_LFXO_BYPASS)
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SUPC->SUPC_MR |= (SUPC_MR_KEY_PASSWD | SUPC_MR_OSCBYPASS);
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else
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SUPC->SUPC_MR = (SUPC->SUPC_MR & ~SUPC_MR_OSCBYPASS) | SUPC_MR_KEY_PASSWD;
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if (src == PMC_SCLK_LFRCO)
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SUPC->SUPC_CR = (SUPC->SUPC_CR & ~SUPC_CR_XTALSEL) | SUPC_CR_KEY_PASSWD;
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else
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SUPC->SUPC_CR |= (SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL);
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}
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void pmc_mainck_source_set(enum pmc_mainck_src_t src)
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{
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u32 ckgr_mor_val = 0;
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if (src == PMC_MAINCK_HFXO)
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ckgr_mor_val = CKGR_MOR_MOSCSEL;
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PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | CKGR_MOR_KEY_PASSWD | ckgr_mor_val;
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}
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void pmc_mck_source_set(enum pmc_mck_src_t src, u8 prescaler)
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{
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if (!prescaler)
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prescaler = 1;
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u32 pmc_mckr_val = 0;
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if (src == PMC_MCK_UPLLCK2)
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pmc_mckr_val = PMC_MCKR_UPLLDIV2;
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PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(PMC_MCKR_PRES_Msk | PMC_MCKR_CSS_Msk)) | PMC_MCKR_CSS(src) |
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PMC_MCKR_PRES(prescaler - 1) | pmc_mckr_val;
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) continue;
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}
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void pmc_peripheral_clock_enable(u8 pid)
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{
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if (pid > 31)
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return;
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PMC->PMC_PCER0 = 1 << pid;
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}
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void pmc_peripheral_clock_disable(u8 pid)
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{
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if (pid > 31)
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return;
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PMC->PMC_PCDR0 = 1 << pid;
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}

‎src/platform/sam3u/pmc.h‎

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/*
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* SPDX-License-Identifier: MIT
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* SPDX-FileCopyrightText: 2021 Rafael Silva <perigoso@riseup.net>
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*/
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#pragma once
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#include "sam.h"
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#include <stdbool.h>
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#include "util/types.h"
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struct pmc_clock_tree_t {
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u32 hfxo_freq;
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u32 hfrco_freq;
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u32 lfxo_freq;
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u32 lfrco_freq;
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u32 slck_freq;
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u32 mainck_freq;
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u32 pllack_freq;
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u32 upllck_freq;
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u32 mck_freq;
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u32 fclk_freq;
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};
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enum pmc_hfrco_freq_t {
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PMC_HFRCO_4MHZ = 0x0u,
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PMC_HFRCO_8MHZ = 0x1u,
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PMC_HFRCO_12MHZ = 0x2u,
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};
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enum pmc_slck_src_t {
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PMC_SCLK_LFRCO = 0,
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PMC_SCLK_LFXO = 1,
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PMC_SCLK_LFXO_BYPASS = 2,
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};
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enum pmc_mainck_src_t {
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PMC_MAINCK_HFRCO = 0,
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PMC_MAINCK_HFXO = 1,
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};
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enum pmc_mck_src_t {
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PMC_MCK_SLCK = 0x0u,
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PMC_MCK_MAINCK = 0x1u,
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PMC_MCK_PLLACK = 0x2u,
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PMC_MCK_UPLLCK2 = 0x3u,
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};
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void pmc_init(u32 hfxo_freq, u32 lfxo_freq);
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void pmc_update_clock_tree();
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const struct pmc_clock_tree_t *pmc_get_clock_tree();
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void pmc_hfxo_enable(bool bypass, u8 startup_time);
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void pmc_hfxo_disable();
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void pmc_hfrco_enable(enum pmc_hfrco_freq_t freq);
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void pmc_hfrco_disable();
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void pmc_pllack_enable(u8 mul, u8 div);
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void pmc_pllack_disable();
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void pmc_upllck_enable();
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void pmc_upllck_disable();
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void pmc_slck_source_set(enum pmc_slck_src_t src);
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void pmc_mainck_source_set(enum pmc_mainck_src_t src);
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void pmc_mck_source_set(enum pmc_mck_src_t src, u8 prescaler);
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void pmc_peripheral_clock_enable(u8 pid);
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void pmc_peripheral_clock_disable(u8 pid);

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