Skip to content

Commit cecdba0

Browse files
fvalette-ledgerfvalette-ledger
authored
Add stm32wb soc family (#114)
2 parents 36089c7 + b2e30c7 commit cecdba0

File tree

14 files changed

+394
-9
lines changed

14 files changed

+394
-9
lines changed

‎.github/workflows/gnulinux.yml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,11 @@ jobs:
2929
if "${{ github.event_name }}" == "pull_request":
3030
operating_system = [ 'mesonbuild/ubuntu-rolling', 'mesonbuild/arch:latest' ]
3131
toolchain = [ 'gcc|12.3.Rel1', 'gcc|10.3-2021.07', 'gcc|13.2.Rel1' ]
32-
config = [ 'nucleo_u5a5_autotest', 'nucleo_u5a5_nooutput', 'stm32f429i_disc1_debug', 'stm32f429i_disc1_release', 'stm32f429i_disc1_autotest' ]
32+
config = [ 'nucleo_u5a5_autotest', 'nucleo_wb55_autotest', 'nucleo_u5a5_nooutput', 'stm32f429i_disc1_debug', 'stm32f429i_disc1_release', 'stm32f429i_disc1_autotest' ]
3333
else:
3434
operating_system = [ 'mesonbuild/ubuntu-rolling' ]
3535
toolchain = [ 'gcc|12.3.Rel1' ]
36-
config = [ 'nucleo_u5a5_autotest', 'stm32f429i_disc1_debug', 'nucleo_l476rg_debug', 'nucleo_f401re' ]
36+
config = [ 'nucleo_u5a5_autotest', 'nucleo_wb55_autotest', 'stm32f429i_disc1_debug', 'nucleo_l476rg_debug', 'nucleo_f401re' ]
3737
with open(os.environ['GITHUB_OUTPUT'], 'w') as gh_out:
3838
gh_out.write(f"operating_system={operating_system}\n")
3939
gh_out.write(f"toolchain={toolchain}\n")

‎configs/nucleo_wb55_autotest_defconfig‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
# SPDX-FileCopyrightText: 2025 Ledger SAS
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
CONFIG_ARCH_MCU_STM32WB55_CM4=y
5+
CONFIG_DRV_STM32_LPUART=y
6+
CONFIG_STANDALONE_MODE=y
7+
CONFIG_BUILD_TARGET_AUTOTEST=y
8+
# CONFIG_TEST_SHM is not set

‎dts/examples/nucleo_wb55_autotest.dts‎

Lines changed: 129 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,129 @@
1+
/*
2+
* Copyright (c) 2025 Ledger SAS
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/dts-v1/;
8+
9+
#include <st/wb/stm32wb55Xg.dtsi>
10+
#include <dt-bindings/pinctrl/stm32-pinctrl.h>
11+
#include <sentry.dtsi>
12+
13+
/{
14+
chosen {
15+
sentry,debug_stdout = <&lpuart1>;
16+
sentry,autotestram_section = <&autotest_ram>;
17+
sentry,autotestcode_section = <&autotest_code>;
18+
};
19+
};
20+
21+
/{
22+
reserved-memory {
23+
autotest_code: autotest_code@800d000 {
24+
reg = <0x8010000 0xe000>;
25+
compatible = "outpost,memory-pool";
26+
};
27+
28+
autotest_ram: autotest_memory@20008000 {
29+
reg = <0x20008000 0x1000>;
30+
compatible = "outpost,memory-pool";
31+
};
32+
};
33+
};
34+
35+
&flash0 {
36+
reg = <0x08000000 DT_SIZE_M(1)>;
37+
};
38+
39+
&sram0 {
40+
reg = <0x20000000 DT_SIZE_K(192)>;
41+
};
42+
43+
44+
&flash {
45+
wait-state = <3>; /* According to voltage supply and sysclock */
46+
status = "okay";
47+
};
48+
49+
&clk_lsi1 {
50+
status = "okay";
51+
};
52+
53+
&clk_hsi {
54+
status = "okay";
55+
};
56+
57+
&clk_hsi48 {
58+
status = "okay";
59+
};
60+
61+
&clk_msi {
62+
status = "okay";
63+
};
64+
65+
&pll {
66+
status = "okay";
67+
};
68+
69+
&rcc {
70+
clocks = <&pll>;
71+
clock-frequency = <DT_FREQ_M(64)>;
72+
bus-prescalers = <0>, <0>, <0>;
73+
bus-names = "ahb", "apb1", "apb2";
74+
status = "okay";
75+
};
76+
77+
&gpioa {
78+
status = "okay";
79+
};
80+
81+
&gpiob {
82+
status = "okay";
83+
};
84+
85+
&gpioc {
86+
status = "okay";
87+
};
88+
89+
&gpiod {
90+
status = "okay";
91+
};
92+
93+
&gpioe {
94+
status = "okay";
95+
};
96+
97+
&exti {
98+
events = <49>;
99+
status = "okay";
100+
};
101+
102+
&rng {
103+
status = "okay";
104+
};
105+
106+
&syscfg {
107+
status = "okay";
108+
};
109+
110+
&lpuart1{
111+
status = "okay";
112+
pinctrl-0 = <&lpuart1_tx>, <&lpuart1_rx>;
113+
};
114+
115+
&pinctrl {
116+
lpuart1_tx: lpuart1_tx {
117+
pinmux = <&gpioa 2 STM32_DT_PIN_MODE_ALTFUNC(8)>;
118+
pincfg = <STM32_OTYPER_PUSH_PULL \
119+
STM32_OSPEEDR_VERY_HIGH_SPEED \
120+
STM32_PUPDR_NO_PULL>;
121+
};
122+
123+
lpuart1_rx: lpuart1_rx {
124+
pinmux = <&gpioa 3 STM32_DT_PIN_MODE_ALTFUNC(8)>;
125+
pincfg = <STM32_OTYPER_PUSH_PULL \
126+
STM32_OSPEEDR_VERY_HIGH_SPEED \
127+
STM32_PUPDR_NO_PULL>;
128+
};
129+
};

‎kernel/include/bsp/drivers/clk/pwr.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,16 @@ typedef enum clk_vos_scale {
6565
s == POWER_VOS_SCALE_2 ||
6666
s == POWER_VOS_SCALE_1;
6767
*/
68+
#elif defined(CONFIG_SOC_SUBFAMILY_STM32WB)
69+
typedef enum clk_vos_scale {
70+
POWER_VOS_SCALE_1 = 0x1UL,
71+
POWER_VOS_SCALE_2 = 0x2UL,
72+
} clk_vos_scale_t;
73+
/*@
74+
predicate scale_is_valid(uint8_t s) =
75+
s == POWER_VOS_SCALE_2 ||
76+
s == POWER_VOS_SCALE_1;
77+
*/
6878
#endif
6979
kstatus_t pwr_probe(void);
7080

‎kernel/include/sentry/arch/asm-cortex-m/meson.build‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,8 @@ buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32L4', if_true: files('stm32l4
6161
# see: https://git.orange.ledgerlabs.net/outpost/sentry-kernel/issues/188
6262
# rework this as this is weak
6363
buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32U5', if_true: files('stm32l4-buses.h.in'))
64+
buses_h_in_set.add(when: 'CONFIG_SOC_SUBFAMILY_STM32WB', if_true: files('stm32l4-buses.h.in'))
65+
6466
# here, we can add other templates for other ARM SoC famillies if needed
6567
buses_h_in_set_config = buses_h_in_set.apply(kconfig_data, strict: false)
6668

‎kernel/src/arch/asm-cortex-m/Kconfig‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,6 +166,7 @@ config SOC_SUBFAMILY_STM32WB
166166
select SOC_FAMILY_STM32
167167
select HAS_FPU
168168
select HAS_MPU
169+
select HAS_RNG
169170
select HAS_MPU_PMSA_V7
170171
# Cache support ?
171172
help
@@ -218,7 +219,7 @@ config ARCH_ARM_CORTEX_NAME
218219

219220
config ARCH_SOCNAME
220221
string
221-
default "STM32WB55" if ARCH_MCU_STM32WB55
222+
default "STM32WB55_CM4" if ARCH_MCU_STM32WB55_CM4
222223
default "STM32F401" if ARCH_MCU_STM32F401
223224
default "STM32F407" if ARCH_MCU_STM32F407
224225
default "STM32F419" if ARCH_MCU_STM32F419
@@ -259,7 +260,7 @@ config ARCH_MCU_STM32F401
259260
bool "STM32F401"
260261
select SOC_SUBFAMILY_STM32F4
261262

262-
config ARCH_MCU_STM32WB55
263+
config ARCH_MCU_STM32WB55_CM4
263264
bool "STM32WB55"
264265
select SOC_SUBFAMILY_STM32WB
265266

‎kernel/src/drivers/clk/meson.build‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,21 @@ stm32u5_rcc_h = dtsgen.process(
146146
bsp_clk_private_gen_header_set.add(stm32u5_rcc_h)
147147
endif
148148

149+
if kconfig_data.get('CONFIG_SOC_SUBFAMILY_STM32WB', 0) == 1
150+
stm32wb_rcc_c_template = files('stm32wb-rcc.c.in')
151+
stm32wb_rcc_c = dtsgen.process(
152+
stm32wb_rcc_c_template,
153+
preserve_path_from: meson.current_source_dir(),
154+
)
155+
bsp_clk_private_gen_source_set.add(stm32wb_rcc_c)
156+
stm32wb_rcc_h_template = files('stm32wb-rcc.h.in')
157+
stm32wb_rcc_h = dtsgen.process(
158+
stm32wb_rcc_h_template,
159+
preserve_path_from: meson.current_source_dir(),
160+
)
161+
bsp_clk_private_gen_header_set.add(stm32wb_rcc_h)
162+
endif
163+
149164
pwr_h = custom_target('gen_pwr',
150165
input: peripheral_defs_in,
151166
output: '@0@_defs.h'.format('pwr'),

‎kernel/src/drivers/clk/stm32-pwr.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
#include "pwr_defs.h"
2020

2121
/* TODO: move stm32l4/f4 in a dedicated file */
22-
#if defined(CONFIG_SOC_SUBFAMILY_STM32L4)
22+
#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32WB)
2323
#define PWR_CR_REG PWR_CR1_REG
2424
#define PWR_CR_VOS_MASK PWR_CR1_VOS_MASK
2525
#define PWR_CR_VOS_SHIFT PWR_CR1_VOS_SHIFT
@@ -28,7 +28,7 @@
2828
#endif
2929

3030
/* FIXME */
31-
#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32F4)
31+
#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32F4) || defined(CONFIG_SOC_SUBFAMILY_STM32WB)
3232
# if defined(CONFIG_ARCH_MCU_STM32F401)
3333
# define DEFAULT_SCALE_MODE POWER_VOS_SCALE_2
3434
# else
@@ -59,7 +59,7 @@ kstatus_t pwr_probe(void)
5959
return pwr_set_voltage_regulator_scaling(DEFAULT_SCALE_MODE);
6060
}
6161

62-
#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32F4)
62+
#if defined(CONFIG_SOC_SUBFAMILY_STM32L4) || defined(CONFIG_SOC_SUBFAMILY_STM32F4) || defined(CONFIG_SOC_SUBFAMILY_STM32WB)
6363
/*@
6464
requires scale_is_valid(scale);
6565
ensures \result == K_STATUS_OKAY;

‎kernel/src/drivers/clk/stm32-rcc.c.in‎

Lines changed: 25 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,8 @@
3131
#include "stm32l4-rcc.h"
3232
#elif defined(CONFIG_SOC_SUBFAMILY_STM32U5)
3333
#include "stm32u5-rcc.h"
34+
#elif defined(CONFIG_SOC_SUBFAMILY_STM32WB)
35+
#include "stm32wb-rcc.h"
3436
#endif
3537

3638
#include "stm32-rcc.h"
@@ -333,10 +335,18 @@ __STATIC_INLINE size_t rcc_get_register(bus_id_t busid, rcc_opts_t flags)
333335
reg_base = RCC_BASE_ADDR;
334336
}
335337

338+
/* XXX:
339+
* As bus ID comes from DTS and this test function is based on DTS too
340+
* One can assume that this is consistent.
341+
* TODO:
342+
* To be refined
343+
*/
344+
#if 0
336345
if (unlikely(!BUS_IS_VALID(busid))) {
337346
/* FIXME: status (error) should be returned instead */
338-
return 0;
347+
// return 0;
339348
}
349+
#endif
340350
/*@ assert bus_is_valid(busid); */
341351
reg_base += busid;
342352

@@ -369,9 +379,17 @@ kstatus_t rcc_enable(bus_id_t busid, uint32_t clk_msk, rcc_opts_t flags)
369379
goto err;
370380
}
371381

382+
/* XXX:
383+
* As bus ID comes from DTS and this test function is based on DTS too
384+
* One can assume that this is consistent.
385+
* TODO:
386+
* To be refined
387+
*/
388+
#if 0
372389
if (unlikely(!BUS_IS_VALID(busid))) {
373390
goto err;
374391
}
392+
#endif
375393
/*@ assert bus_is_valid(busid); */
376394
size_t reg_base = rcc_get_register(busid, flags);
377395

@@ -453,6 +471,9 @@ kstatus_t rcc_get_bus_clock(bus_id_t busid, uint32_t *busclk)
453471
/*@ assert bus_is_valid(busid); */
454472
switch (busid) {
455473
case BUS_APB1:
474+
#if defined(HAS_BUS_APB1_2)
475+
case BUS_APB1 + 4:
476+
#endif
456477
*busclk = RCC_APB1_CLOCK_FREQUENCY;
457478
break;
458479
case BUS_APB2:
@@ -466,6 +487,9 @@ kstatus_t rcc_get_bus_clock(bus_id_t busid, uint32_t *busclk)
466487
case BUS_AHB1:
467488
#if defined(HAS_BUS_AHB2)
468489
case BUS_AHB2:
490+
#if defined(HAS_BUS_AHB2_2)
491+
case BUS_AHB2 + 4:
492+
#endif
469493
#endif
470494
#if defined(HAS_BUS_AHB3)
471495
case BUS_AHB3:

‎kernel/src/drivers/clk/stm32l4-rcc.h.in‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,8 @@
8181
#define RCC_HSI48RDY RCC_CRRCR_HSI48RDY
8282
#endif
8383

84+
#define HAS_BUS_APB1_2
85+
8486
{#- There is only one main PLL for stm32f4xx families #}
8587
{%- set pll = dts.get_compatible("st,stm32l4xx-pll")[0] %}
8688
{%- if pll is not none and pll.status == "okay"%}

0 commit comments

Comments
 (0)