Not code issue but issue with wiki for HiLetgo PCM5102 I2S IIS Lossless Digital Audio DAC Decoder #708
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Problem DescriptionWish there was a better way to comment this as it is not an issue with your code but wanted to give a quick heads up. On your DAC wiki's for the HiLetgo PCM5102 I2S IIS Lossless Digital Audio DAC Decoder. There are a ton of copies of this module on amazon that are not HiLetgo. I have been struggling to get them working and just learned that on those the sck needs to go to 5v not gnd per your wiki. Understood your wiki is for HiLetgo PCM5102 I2S IIS Lossless Digital Audio DAC Decoder and that it is probably correct for that just thought I would give my experience with off brand as I have been banging my head trying to get it to work figured others were too. Device DescriptionPCM5102 I2S IIS Lossless Digital Audio DAC Decoder with ESP32 SketchSee above not code related but was not sure where to add the comment in repo besides here. Other Steps to ReproduceNo response Provide your Version of the EP32 Arduino Core (or the IDF Version)2.3.4 I have checked existing issues, discussions and online documentation
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Replies: 3 comments 6 replies
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I am afraid this does not make any sense. Here is the info from the Technical Sheet: System Clock PLL ModeThe system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the DAC. So as a conclusion you either connect the master clock pin from the ESP32 or you have leave it low. Did you double check the solder bridges against the recommended values ? |
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I have updated the documentation. Did you try to leave it unconnected ? |
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from the amazon picture it looks like the sck-gnd solder bridge is preconnected with a small resistor because most people need that anyways. If you need to use an external clock with these modules the best would be to remove that bridge and not to provide 5V and have a permanent unknown but potentially high current |
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I am afraid this does not make any sense. Here is the info from the Technical Sheet:
System Clock PLL Mode
The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the DAC.
The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high
frequency electromagnetic interference.
The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at
ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal
SCK from the BCK reference. The PCM510x disables the internal PLL when an external SCK is supplied;
specific BCK rates…