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Not code issue but issue with wiki for HiLetgo PCM5102 I2S IIS Lossless Digital Audio DAC Decoder #708

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I am afraid this does not make any sense. Here is the info from the Technical Sheet:

System Clock PLL Mode

The system clock PLL mode allows designers to use a simple 3-wire I2S audio source when driving the DAC.
The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high
frequency electromagnetic interference.
The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at
ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal
SCK from the BCK reference. The PCM510x disables the internal PLL when an external SCK is supplied;
specific BCK rates…

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@pschatzmann
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Converted from issue

This discussion was converted from issue #707 on May 11, 2025 06:47.