treewide: Replace hjson and reggen with rdl and peakrdl

Author: micprog

.github/workflows/ci.yml

@@ -69,7 +69,7 @@ jobs:
     container:
       image: ${{ needs.build-docker.outputs.image_name }}
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
       - name: Build docs
         run: make docs
 
@@ -81,7 +81,7 @@ jobs:
     container:
       image: ${{ needs.build-docker.outputs.image_name }}
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
       # For some reason, the checkout is done by a different user
       # than that deploying to Github (root, possibly due to Docker).
       # So we need to set the repository as a safe directory.
@@ -106,7 +106,7 @@ jobs:
     container:
       image: ${{ needs.build-docker.outputs.image_name }}
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
       - name: Run pytest
         run: pytest
 
@@ -121,7 +121,7 @@ jobs:
     container:
       image: ${{ needs.build-docker.outputs.image_name }}
     steps:
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v4
         with:
           submodules: 'recursive'
       - name: Hash Verilator prerequisites
@@ -133,7 +133,7 @@ jobs:
           flags: --recursive
       - name: Set up cache for Verilator build
         id: verilator-cache
-        uses: actions/cache@v3
+        uses: actions/cache@v4
         with:
           path: target/snitch_cluster/bin
           key: verilator-${{ steps.verilator-hash.outputs.hash }}

.github/workflows/gitlab-ci.yaml

@@ -16,7 +16,7 @@ jobs:
       github.repository == 'pulp-platform/snitch_cluster'
     steps:
       - name: Check Gitlab CI
-        uses: pulp-platform/pulp-actions/gitlab-ci@v2.1.0
+        uses: pulp-platform/pulp-actions/gitlab-ci@v2.4.3
         with:
           domain: iis-git.ee.ethz.ch
           repo: github-mirror/snitch_cluster

.github/workflows/lint.yml

@@ -18,7 +18,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - uses: chipsalliance/verible-linter-action@main
         with:
           paths: |
@@ -53,9 +53,9 @@ jobs:
       github.event.pull_request.head.repo.full_name != github.repository
     steps:
       - name: Check License
-        uses: pulp-platform/pulp-actions/lint-license@v2.1.0
+        uses: pulp-platform/pulp-actions/lint-license@v2.4.3
         with:
-          patches: 0001-Allow-hash-comments-in-assembly.patch
+          linters_revision: 20250217_01
           # We cover ETH Zurich and lowRISC licenses and Apache 2.0
           # (mostly for SW) and Solderpad for the hardware.
           # yamllint disable rule:line-length
@@ -67,6 +67,9 @@ jobs:
           match_regex: true
           exclude_paths: |
             sw/snRuntime/src/omp/interface.h
+            hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv
+            hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv
+            hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.svh
 
   ##################
   # Lint YML Files #
@@ -78,7 +81,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     steps:
-      - uses: actions/checkout@v3
+      - uses: actions/checkout@v4
       - name: yaml-lint
         uses: ibiqlik/action-yamllint@v3
         with:
@@ -95,9 +98,9 @@ jobs:
     name: Lint Python Sources
     steps:
       - name: Check out source repository
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
       - name: Set up Python environment
-        uses: actions/setup-python@v4
+        uses: actions/setup-python@v5
         with:
           python-version: "3.11"
       - name: flake8 Lint
@@ -117,7 +120,7 @@ jobs:
       github.event_name != 'pull_request' ||
       github.event.pull_request.head.repo.full_name != github.repository
     steps:
-      - uses: actions/checkout@v3
-      - uses: DoozyX/clang-format-lint-action@v0.18.1
+      - uses: actions/checkout@v4
+      - uses: DoozyX/clang-format-lint-action@v0.18.2
         with:
           clangFormatVersion: 10

Bender.lock

@@ -83,8 +83,8 @@ packages:
     - obi
     - register_interface
   obi:
-    revision: 8097928cf1b43712f93d5356f336397879b4ad2c
-    version: 0.1.6
+    revision: 0155fc34e900c7c884e081c0a1114a247937ff69
+    version: 0.1.7
     source:
       Git: https://github.com/pulp-platform/obi.git
     dependencies:
@@ -94,7 +94,7 @@ packages:
     revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
     version: 0.4.5
     source:
-      Git: https://github.com/pulp-platform/register_interface
+      Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
     - apb
     - axi

Bender.yml

@@ -22,8 +22,8 @@ dependencies:
   axi:                { git: https://github.com/colluca/axi,                      rev:  multicast       }
   axi_riscv_atomics:  { git: https://github.com/pulp-platform/axi_riscv_atomics,  version:  0.6.0       }
   common_cells:       { git: https://github.com/pulp-platform/common_cells,       rev:      snitch      }
+  apb:                { git: https://github.com/pulp-platform/apb.git,            version:  0.2.2       }
   FPnew:              { git: https://github.com/pulp-platform/cvfpu.git,          rev:      pulp-v0.1.3 }
-  register_interface: { git: https://github.com/pulp-platform/register_interface, version:  0.4.2       }
   tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version:  0.2.13      }
   riscv-dbg:          { git: https://github.com/pulp-platform/riscv-dbg,          version:  0.8.0       }
   cluster_icache:     { git: https://github.com/pulp-platform/cluster_icache.git, rev: 64e21ae455bbdde850c4df13bef86ea55ac42537 }
@@ -155,7 +155,7 @@ sources:
       # Level 0
       - hw/snitch_cluster/src/snitch_amo_shim.sv
       - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_pkg.sv
-      - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg_top.sv
+      - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.sv
       - hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral.sv
       - hw/snitch_cluster/src/snitch_fpu.sv
       - hw/snitch_cluster/src/snitch_sequencer.sv
@@ -180,7 +180,6 @@ sources:
   # target/common
   - target: any(simulation, verilator)
     files:
-      - target/common/test/tb_memory_regbus.sv
       - target/common/test/tb_memory_axi.sv
   - target: test
     files:

Makefile

@@ -7,7 +7,7 @@
 ###############
 
 BENDER ?= bender
-REGGEN  = $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/regtool.py
+PEAKRDL ?= peakrdl
 
 #########################
 # Files and directories #
@@ -80,8 +80,8 @@ clean-docs:
 $(GENERATED_DOCS_DIR):
 	mkdir -p $@
 
-$(GENERATED_DOCS_DIR)/peripherals.md: hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.hjson | $(GENERATED_DOCS_DIR)
-	$(REGGEN) -d $< > $@
+$(GENERATED_DOCS_DIR)/peripherals.md: hw/snitch_cluster/src/snitch_cluster_peripheral/snitch_cluster_peripheral_reg.rdl | $(GENERATED_DOCS_DIR)
+	$(PEAKRDL) markdown $< -o $@
 
 $(DOXYGEN_DOCS_DIR): $(DOXYFILE) $(DOXYGEN_INPUTS)
 	doxygen $<

hw/snitch_cluster/src/snitch_cluster.sv

@@ -12,7 +12,7 @@
 `include "common_cells/registers.svh"
 
 `include "mem_interface/typedef.svh"
-`include "register_interface/typedef.svh"
+`include "apb/typedef.svh"
 `include "reqrsp_interface/typedef.svh"
 `include "tcdm_interface/typedef.svh"
 
@@ -426,16 +426,17 @@ module snitch_cluster
   `AXI_TYPEDEF_ALL(axi_mst_dma, addr_t, id_dma_mst_t, data_dma_t, strb_dma_t, user_dma_t)
   `AXI_TYPEDEF_ALL(axi_slv_dma, addr_t, id_dma_slv_t, data_dma_t, strb_dma_t, user_dma_t)
 
+  `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t)
+
+  `APB_TYPEDEF_ALL(apb, addr_t, data_t, strb_t)
+
   `REQRSP_TYPEDEF_ALL(reqrsp, addr_t, data_t, strb_t)
 
   `MEM_TYPEDEF_ALL(mem, tcdm_mem_addr_t, data_t, strb_t, tcdm_user_t)
   `MEM_TYPEDEF_ALL(mem_dma, tcdm_mem_addr_t, data_dma_t, strb_dma_t, logic)
 
   `TCDM_TYPEDEF_ALL(tcdm, tcdm_addr_t, data_t, strb_t, tcdm_user_t)
 
-  `REG_BUS_TYPEDEF_REQ(reg_req_t, addr_t, data_t, strb_t)
-  `REG_BUS_TYPEDEF_RSP(reg_rsp_t, data_t)
-
   // Event counter increments for the TCDM.
   typedef struct packed {
     /// Number requests going in
@@ -602,8 +603,10 @@ module snitch_cluster
   reqrsp_rsp_t [NrHives-1:0] ptw_rsp;
 
   // 5. Peripheral Subsystem
-  reg_req_t reg_req;
-  reg_rsp_t reg_rsp;
+  axi_lite_req_t axi_lite_req;
+  axi_lite_resp_t axi_lite_resp;
+  apb_req_t apb_req;
+  apb_resp_t apb_resp;
 
   // 5. Misc. Wires.
   logic icache_prefetch_enable;
@@ -1372,26 +1375,59 @@ module snitch_cluster
   );
 
   // 2. Peripherals
-  axi_to_reg #(
-    .ADDR_WIDTH (PhysicalAddrWidth),
-    .DATA_WIDTH (NarrowDataWidth),
-    .AXI_MAX_WRITE_TXNS (1),
-    .AXI_MAX_READ_TXNS (1),
-    .DECOUPLE_W (0),
-    .ID_WIDTH (NarrowIdWidthOut),
-    .USER_WIDTH (NarrowUserWidth),
-    .axi_req_t (axi_slv_req_t),
-    .axi_rsp_t (axi_slv_resp_t),
-    .reg_req_t (reg_req_t),
-    .reg_rsp_t (reg_rsp_t)
-  ) i_axi_to_reg (
-    .clk_i,
-    .rst_ni,
-    .testmode_i (1'b0),
-    .axi_req_i (narrow_axi_slv_req[ClusterPeripherals]),
-    .axi_rsp_o (narrow_axi_slv_rsp[ClusterPeripherals]),
-    .reg_req_o (reg_req),
-    .reg_rsp_i (reg_rsp)
+  axi_to_axi_lite #(
+    .AxiAddrWidth   (PhysicalAddrWidth),
+    .AxiDataWidth   (NarrowDataWidth),
+    .AxiIdWidth     (NarrowIdWidthOut),
+    .AxiUserWidth   (NarrowUserWidth),
+    .AxiMaxWriteTxns(1),
+    .AxiMaxReadTxns (1),
+    .full_req_t     (axi_slv_req_t),
+    .full_resp_t    (axi_slv_resp_t),
+    .lite_req_t     (axi_lite_req_t),
+    .lite_resp_t    (axi_lite_resp_t)
+  ) i_axi_to_axi_lite (
+    .clk_i     (clk_i),
+    .rst_ni    (rst_ni),
+    .test_i    (1'b0),
+    .slv_req_i (narrow_axi_slv_req[ClusterPeripherals]),
+    .slv_resp_o(narrow_axi_slv_rsp[ClusterPeripherals]),
+    .mst_req_o (axi_lite_req),
+    .mst_resp_i(axi_lite_resp)
+  );
+
+  // There is only one APB slave in the cluster, at index 0.
+  localparam int unsigned NumApbSlaves = 1;
+  localparam int unsigned NumApbConvRules = (1 + AliasRegionEnable) * NumApbSlaves;
+  xbar_rule_t [NumApbConvRules-1:0] apb_conv_rules;
+
+  assign apb_conv_rules[0] = '{
+    idx: 0, start_addr: cluster_periph_start_address, end_addr: cluster_periph_end_address
+  };
+  if (AliasRegionEnable) begin : gen_apb_alias
+    assign apb_conv_rules[1] = '{
+      idx: 0, start_addr: PeriphAliasStart, end_addr: PeriphAliasEnd
+    };
+  end
+
+  axi_lite_to_apb #(
+    .NoApbSlaves     (NumApbSlaves),
+    .NoRules         (NumApbConvRules),
+    .AddrWidth       (PhysicalAddrWidth),
+    .DataWidth       (NarrowDataWidth),
+    .axi_lite_req_t  (axi_lite_req_t),
+    .axi_lite_resp_t (axi_lite_resp_t),
+    .apb_req_t       (apb_req_t),
+    .apb_resp_t      (apb_resp_t),
+    .rule_t          (xbar_rule_t)
+  ) i_axi_lite_to_apb (
+    .clk_i          (clk_i),
+    .rst_ni         (rst_ni),
+    .axi_lite_req_i (axi_lite_req),
+    .axi_lite_resp_o(axi_lite_resp),
+    .apb_req_o      (apb_req),
+    .apb_resp_i     (apb_resp),
+    .addr_map_i     (apb_conv_rules)
   );
 
   if (IntBootromEnable) begin : gen_bootrom
@@ -1440,17 +1476,20 @@ module snitch_cluster
   end
 
   snitch_cluster_peripheral #(
-    .reg_req_t (reg_req_t),
-    .reg_rsp_t (reg_rsp_t),
+    .addr_t (addr_t),
+    .data_t (data_t),
+    .strb_t (strb_t),
+    .apb_req_t (apb_req_t),
+    .apb_resp_t (apb_resp_t),
     .tcdm_events_t (tcdm_events_t),
     .dma_events_t (dma_events_t),
     .NrCores (NrCores),
     .DMANumChannels (DMANumChannels)
   ) i_snitch_cluster_peripheral (
     .clk_i,
     .rst_ni,
-    .reg_req_i (reg_req),
-    .reg_rsp_o (reg_rsp),
+    .apb_req_i (apb_req),
+    .apb_resp_o (apb_resp),
     .icache_prefetch_enable_o (icache_prefetch_enable),
     .cl_clint_o (cl_interrupt),
     .core_events_i (core_events),