Skip to content

Commit 4c932cf

Browse files
aswatermanaswaterman
authored
Merge pull request #1882 from fk-sc/fk-sc/mprven-support
Add DCSR.MPRVEN support
2 parents ba54a60 + 9b2a1d6 commit 4c932cf

File tree

5 files changed

+74
-22
lines changed

5 files changed

+74
-22
lines changed

‎debug_rom/debug_rom.S‎

Lines changed: 47 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,19 @@
77
.global entry
88
.global exception
99

10+
// This macro handles mem access with proper management of the MPRVEN
11+
// Usage: MEMORY_ACCESS_WITH_MPRV(<your code>)
12+
#define MEMORY_ACCESS_WITH_MPRV(...) \
13+
csrrci s0, CSR_DCSR, DCSR_MPRVEN; \
14+
andi s0, s0, DCSR_MPRVEN; \
15+
bnez s0, 1f; \
16+
__VA_ARGS__; \
17+
j 2f; \
18+
1: \
19+
__VA_ARGS__; \
20+
csrrsi zero, CSR_DCSR, DCSR_MPRVEN; \
21+
2:
22+
1023
// Entry location on ebreak, Halt, or Breakpoint
1124
// It is the same for all harts. They branch when
1225
// their GO or RESUME bit is set.
@@ -30,13 +43,22 @@ _entry:
3043
// We keep checking both whether there is something the debugger wants
3144
// us to do, or whether we should resume.
3245
entry_loop:
33-
csrr s0, CSR_MHARTID
34-
sw s0, DEBUG_ROM_HALTED(zero)
35-
lbu s0, DEBUG_ROM_FLAGS(s0) // 1 byte flag per hart. Only one hart advances here.
46+
// 1 byte flag per hart. Only one hart advances here.
47+
MEMORY_ACCESS_WITH_MPRV(
48+
csrr s0, CSR_MHARTID;
49+
sw s0, DEBUG_ROM_HALTED(zero);
50+
lbu s0, DEBUG_ROM_FLAGS(s0);
51+
)
52+
3653
andi s0, s0, (1 << DEBUG_ROM_FLAG_GO)
3754
bnez s0, going
38-
csrr s0, CSR_MHARTID
39-
lbu s0, DEBUG_ROM_FLAGS(s0) // multiple harts can resume here
55+
56+
// multiple harts can resume here
57+
MEMORY_ACCESS_WITH_MPRV(
58+
csrr s0, CSR_MHARTID;
59+
lbu s0, DEBUG_ROM_FLAGS(s0);
60+
)
61+
4062
andi s0, s0, (1 << DEBUG_ROM_FLAG_RESUME)
4163
bnez s0, _resume
4264
wfi
@@ -46,13 +68,23 @@ _exception:
4668
// Restore S0, which we always save to dscratch.
4769
// We need this in case the user tried an abstract write to a
4870
// non-existent CSR.
49-
csrr s0, CSR_DSCRATCH0
50-
sw zero, DEBUG_ROM_EXCEPTION(zero) // Let debug module know you got an exception.
71+
72+
73+
// Let debug module know you got an exception.
74+
MEMORY_ACCESS_WITH_MPRV(
75+
csrr s0, CSR_DSCRATCH0;
76+
sw zero, DEBUG_ROM_EXCEPTION(zero);
77+
)
78+
5179
ebreak
5280

5381
going:
54-
csrr s0, CSR_MHARTID
55-
sw s0, DEBUG_ROM_GOING(zero) // When debug module sees this write, the GO flag is reset.
82+
// When debug module sees this write, the GO flag is reset.
83+
MEMORY_ACCESS_WITH_MPRV(
84+
csrr s0, CSR_MHARTID;
85+
sw s0, DEBUG_ROM_GOING(zero);
86+
)
87+
5688
csrr s0, CSR_DSCRATCH0 // Restore s0 here
5789
fence
5890
fence.i
@@ -61,8 +93,12 @@ going:
6193
// because jalr is special there)
6294

6395
_resume:
64-
csrr s0, CSR_MHARTID
65-
sw s0, DEBUG_ROM_RESUMING(zero) // When Debug Module sees this write, the RESUME flag is reset.
96+
// When Debug Module sees this write, the RESUME flag is reset.
97+
MEMORY_ACCESS_WITH_MPRV(
98+
csrr s0, CSR_MHARTID;
99+
sw s0, DEBUG_ROM_RESUMING(zero);
100+
)
101+
66102
csrr s0, CSR_DSCRATCH0 // Restore s0
67103
dret
68104

‎debug_rom/debug_rom.h‎

Lines changed: 22 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,25 @@
11
static const unsigned char debug_rom_raw[] = {
2-
0x6f, 0x00, 0xc0, 0x00, 0x6f, 0x00, 0x00, 0x06, 0x6f, 0x00, 0x80, 0x03,
3-
0x0f, 0x00, 0xf0, 0x0f, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x40, 0xf1,
4-
0x23, 0x20, 0x80, 0x10, 0x03, 0x44, 0x04, 0x40, 0x13, 0x74, 0x14, 0x00,
5-
0x63, 0x14, 0x04, 0x02, 0x73, 0x24, 0x40, 0xf1, 0x03, 0x44, 0x04, 0x40,
6-
0x13, 0x74, 0x24, 0x00, 0x63, 0x18, 0x04, 0x02, 0x73, 0x00, 0x50, 0x10,
7-
0x6f, 0xf0, 0x9f, 0xfd, 0x73, 0x24, 0x20, 0x7b, 0x23, 0x26, 0x00, 0x10,
8-
0x73, 0x00, 0x10, 0x00, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x22, 0x80, 0x10,
9-
0x73, 0x24, 0x20, 0x7b, 0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x10, 0x00, 0x00,
10-
0x67, 0x00, 0x00, 0x30, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x24, 0x80, 0x10,
2+
0x6f, 0x00, 0xc0, 0x00, 0x6f, 0x00, 0x40, 0x0d, 0x6f, 0x00, 0x40, 0x07,
3+
0x0f, 0x00, 0xf0, 0x0f, 0x73, 0x10, 0x24, 0x7b, 0x73, 0x74, 0x08, 0x7b,
4+
0x13, 0x74, 0x04, 0x01, 0x63, 0x1a, 0x04, 0x00, 0x73, 0x24, 0x40, 0xf1,
5+
0x23, 0x20, 0x80, 0x10, 0x03, 0x44, 0x04, 0x40, 0x6f, 0x00, 0x40, 0x01,
6+
0x73, 0x24, 0x40, 0xf1, 0x23, 0x20, 0x80, 0x10, 0x03, 0x44, 0x04, 0x40,
7+
0x73, 0x60, 0x08, 0x7b, 0x13, 0x74, 0x14, 0x00, 0x63, 0x10, 0x04, 0x06,
8+
0x73, 0x74, 0x08, 0x7b, 0x13, 0x74, 0x04, 0x01, 0x63, 0x18, 0x04, 0x00,
9+
0x73, 0x24, 0x40, 0xf1, 0x03, 0x44, 0x04, 0x40, 0x6f, 0x00, 0x00, 0x01,
10+
0x73, 0x24, 0x40, 0xf1, 0x03, 0x44, 0x04, 0x40, 0x73, 0x60, 0x08, 0x7b,
11+
0x13, 0x74, 0x24, 0x00, 0x63, 0x14, 0x04, 0x06, 0x73, 0x00, 0x50, 0x10,
12+
0x6f, 0xf0, 0xdf, 0xf9, 0x73, 0x74, 0x08, 0x7b, 0x13, 0x74, 0x04, 0x01,
13+
0x63, 0x18, 0x04, 0x00, 0x73, 0x24, 0x20, 0x7b, 0x23, 0x26, 0x00, 0x10,
14+
0x6f, 0x00, 0x00, 0x01, 0x73, 0x24, 0x20, 0x7b, 0x23, 0x26, 0x00, 0x10,
15+
0x73, 0x60, 0x08, 0x7b, 0x73, 0x00, 0x10, 0x00, 0x73, 0x74, 0x08, 0x7b,
16+
0x13, 0x74, 0x04, 0x01, 0x63, 0x18, 0x04, 0x00, 0x73, 0x24, 0x40, 0xf1,
17+
0x23, 0x22, 0x80, 0x10, 0x6f, 0x00, 0x00, 0x01, 0x73, 0x24, 0x40, 0xf1,
18+
0x23, 0x22, 0x80, 0x10, 0x73, 0x60, 0x08, 0x7b, 0x73, 0x24, 0x20, 0x7b,
19+
0x0f, 0x00, 0xf0, 0x0f, 0x0f, 0x10, 0x00, 0x00, 0x67, 0x00, 0x00, 0x30,
20+
0x73, 0x74, 0x08, 0x7b, 0x13, 0x74, 0x04, 0x01, 0x63, 0x18, 0x04, 0x00,
21+
0x73, 0x24, 0x40, 0xf1, 0x23, 0x24, 0x80, 0x10, 0x6f, 0x00, 0x00, 0x01,
22+
0x73, 0x24, 0x40, 0xf1, 0x23, 0x24, 0x80, 0x10, 0x73, 0x60, 0x08, 0x7b,
1123
0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b
1224
};
13-
static const unsigned int debug_rom_raw_len = 116;
25+
static const unsigned int debug_rom_raw_len = 260;

‎riscv/csrs.cc‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1421,6 +1421,7 @@ dcsr_csr_t::dcsr_csr_t(processor_t* const proc, const reg_t addr):
14211421
ebreakvs(false),
14221422
ebreakvu(false),
14231423
v(false),
1424+
mprven(false),
14241425
cause(0),
14251426
ext_cause(0),
14261427
cetrig(0),
@@ -1450,6 +1451,7 @@ reg_t dcsr_csr_t::read() const noexcept {
14501451
result = set_field(result, DCSR_STEP, step);
14511452
result = set_field(result, DCSR_PRV, prv);
14521453
result = set_field(result, CSR_DCSR_V, v);
1454+
result = set_field(result, DCSR_MPRVEN, mprven);
14531455
result = set_field(result, DCSR_PELP, pelp);
14541456
return result;
14551457
}
@@ -1464,6 +1466,7 @@ bool dcsr_csr_t::unlogged_write(const reg_t val) noexcept {
14641466
ebreakvs = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_EBREAKVS) : false;
14651467
ebreakvu = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_EBREAKVU) : false;
14661468
v = proc->extension_enabled('H') ? get_field(val, CSR_DCSR_V) : false;
1469+
mprven = get_field(val, CSR_DCSR_MPRVEN);
14671470
pelp = proc->extension_enabled(EXT_ZICFILP) ?
14681471
static_cast<elp_t>(get_field(val, DCSR_PELP)) : elp_t::NO_LP_EXPECTED;
14691472
cetrig = proc->extension_enabled(EXT_SMDBLTRP) ? get_field(val, DCSR_CETRIG) : false;

‎riscv/csrs.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -725,6 +725,7 @@ class dcsr_csr_t: public csr_t {
725725
bool ebreakvs;
726726
bool ebreakvu;
727727
bool v;
728+
bool mprven;
728729
uint8_t cause;
729730
uint8_t ext_cause;
730731
bool cetrig;

‎riscv/mmu.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -508,7 +508,7 @@ class mmu_t
508508
{
509509
return proc != nullptr
510510
&& !(proc->state.mnstatus && !get_field(proc->state.mnstatus->read(), MNSTATUS_NMIE))
511-
&& !proc->state.debug_mode
511+
&& (!proc->state.debug_mode || get_field(proc->state.dcsr->read(), DCSR_MPRVEN))
512512
&& get_field(proc->state.mstatus->read(), MSTATUS_MPRV);
513513
}
514514

0 commit comments

Comments
 (0)