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src/bsp/device_driver/bcm
src/bsp/device_driver/bcm
src/bsp/device_driver/bcm
08_hw_debug_JTAG/src/bsp/device_driver/bcm
09_privilege_level/src/bsp/device_driver/bcm
10_virtual_mem_part1_identity_mapping/src/bsp/device_driver/bcm
11_exceptions_part1_groundwork/src/bsp/device_driver/bcm
12_integrated_testing/src/bsp/device_driver/bcm
13_exceptions_part2_peripheral_IRQs
src/bsp/device_driver/bcm
14_virtual_mem_part2_mmio_remap
src/bsp/device_driver/bcm
15_virtual_mem_part3_precomputed_tables/src/bsp/device_driver/bcm
16_virtual_mem_part4_higher_half_kernel/src/bsp/device_driver/bcm
X1_JTAG_boot/src/bsp/device_driver/bcm Expand file tree Collapse file tree 18 files changed +20
-104
lines changed Original file line number Diff line number Diff line change @@ -459,7 +459,7 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_g
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diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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--- 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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+++ 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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- @@ -0,0 +1,408 @@
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+ @@ -0,0 +1,402 @@
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+ // SPDX-License-Identifier: MIT OR Apache-2.0
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+ //
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+ // Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
@@ -512,12 +512,6 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_dri
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+ /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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+ /// LCR_H Register.
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+ ///
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- + /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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- + /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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- +
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- + /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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- + /// LCR_H Register.
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- + ///
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+ /// - If the FIFO is disabled, this bit is set when the receive holding register is empty.
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+ /// - If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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+ RXFE OFFSET(4) NUMBITS(1) [],
Original file line number Diff line number Diff line change @@ -47,12 +47,6 @@ register_bitfields! {
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/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
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TXFF OFFSET ( 5 ) NUMBITS ( 1 ) [ ] ,
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- /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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- /// LCR_H Register.
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- ///
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- /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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- /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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-
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
Original file line number Diff line number Diff line change @@ -339,7 +339,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_uart
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diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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--- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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+++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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- @@ -284 ,7 +284 ,7 @@
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+ @@ -278 ,7 +278 ,7 @@
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}
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/// Retrieve a character.
@@ -348,7 +348,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0
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// If RX FIFO is empty,
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if self.registers.FR.matches_all(FR::RXFE::SET) {
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// immediately return in non-blocking mode.
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- @@ -299 ,12 +299 ,7 @@
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+ @@ -293 ,12 +293 ,7 @@
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}
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// Read one character.
@@ -362,7 +362,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0
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// Update statistics.
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self.chars_read += 1;
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- @@ -384 ,14 +379 ,14 @@
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+ @@ -378 ,14 +373 ,14 @@
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impl console::interface::Read for PL011Uart {
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fn read_char(&self) -> char {
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self.inner
Original file line number Diff line number Diff line change @@ -47,12 +47,6 @@ register_bitfields! {
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/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
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TXFF OFFSET ( 5 ) NUMBITS ( 1 ) [ ] ,
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- /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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- /// LCR_H Register.
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- ///
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- /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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- /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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-
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
Original file line number Diff line number Diff line change @@ -408,7 +408,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 07_times
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diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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--- 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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+++ 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
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- @@ -284 ,7 +284 ,7 @@
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+ @@ -278 ,7 +278 ,7 @@
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}
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/// Retrieve a character.
@@ -417,7 +417,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07
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// If RX FIFO is empty,
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if self.registers.FR.matches_all(FR::RXFE::SET) {
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// immediately return in non-blocking mode.
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- @@ -299 ,7 +299 ,12 @@
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+ @@ -293 ,7 +293 ,12 @@
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}
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// Read one character.
@@ -431,7 +431,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07
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// Update statistics.
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self.chars_read += 1;
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- @@ -379 ,14 +384 ,14 @@
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+ @@ -373 ,14 +378 ,14 @@
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impl console::interface::Read for PL011Uart {
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fn read_char(&self) -> char {
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self.inner
Original file line number Diff line number Diff line change @@ -47,12 +47,6 @@ register_bitfields! {
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/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
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TXFF OFFSET ( 5 ) NUMBITS ( 1 ) [ ] ,
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- /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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- /// LCR_H Register.
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- ///
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- /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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- /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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-
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
Original file line number Diff line number Diff line change @@ -47,12 +47,6 @@ register_bitfields! {
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/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
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TXFF OFFSET ( 5 ) NUMBITS ( 1 ) [ ] ,
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- /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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- /// LCR_H Register.
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- ///
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- /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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- /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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-
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
Original file line number Diff line number Diff line change @@ -47,12 +47,6 @@ register_bitfields! {
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/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
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TXFF OFFSET ( 5 ) NUMBITS ( 1 ) [ ] ,
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- /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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- /// LCR_H Register.
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- ///
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- /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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- /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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-
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
Original file line number Diff line number Diff line change @@ -47,12 +47,6 @@ register_bitfields! {
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/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
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TXFF OFFSET ( 5 ) NUMBITS ( 1 ) [ ] ,
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- /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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- /// LCR_H Register.
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- ///
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- /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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- /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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-
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
Original file line number Diff line number Diff line change @@ -47,12 +47,6 @@ register_bitfields! {
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/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
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TXFF OFFSET ( 5 ) NUMBITS ( 1 ) [ ] ,
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- /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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- /// LCR_H Register.
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- ///
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- /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
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- /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
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-
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/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
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/// LCR_H Register.
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///
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