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docs: Remove pl011_uart duplicate comments.
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18 files changed

+20
-104
lines changed

18 files changed

+20
-104
lines changed

05_drivers_gpio_uart/README.md

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -459,7 +459,7 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 05_drivers_g
459459
diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
460460
--- 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
461461
+++ 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
462-
@@ -0,0 +1,408 @@
462+
@@ -0,0 +1,402 @@
463463
+// SPDX-License-Identifier: MIT OR Apache-2.0
464464
+//
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+// Copyright (c) 2018-2021 Andre Richter <andre.o.richter@gmail.com>
@@ -512,12 +512,6 @@ diff -uNr 04_safe_globals/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 05_dri
512512
+ /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
513513
+ /// LCR_H Register.
514514
+ ///
515-
+ /// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
516-
+ /// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
517-
+
518-
+ /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
519-
+ /// LCR_H Register.
520-
+ ///
521515
+ /// - If the FIFO is disabled, this bit is set when the receive holding register is empty.
522516
+ /// - If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
523517
+ RXFE OFFSET(4) NUMBITS(1) [],

05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

06_uart_chainloader/README.md

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -339,7 +339,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 06_uart
339339
diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
340340
--- 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
341341
+++ 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
342-
@@ -284,7 +284,7 @@
342+
@@ -278,7 +278,7 @@
343343
}
344344

345345
/// Retrieve a character.
@@ -348,7 +348,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0
348348
// If RX FIFO is empty,
349349
if self.registers.FR.matches_all(FR::RXFE::SET) {
350350
// immediately return in non-blocking mode.
351-
@@ -299,12 +299,7 @@
351+
@@ -293,12 +293,7 @@
352352
}
353353

354354
// Read one character.
@@ -362,7 +362,7 @@ diff -uNr 05_drivers_gpio_uart/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 0
362362

363363
// Update statistics.
364364
self.chars_read += 1;
365-
@@ -384,14 +379,14 @@
365+
@@ -378,14 +373,14 @@
366366
impl console::interface::Read for PL011Uart {
367367
fn read_char(&self) -> char {
368368
self.inner

06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

07_timestamps/README.md

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -408,7 +408,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_gpio.rs 07_times
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diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
409409
--- 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
410410
+++ 07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs
411-
@@ -284,7 +284,7 @@
411+
@@ -278,7 +278,7 @@
412412
}
413413

414414
/// Retrieve a character.
@@ -417,7 +417,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07
417417
// If RX FIFO is empty,
418418
if self.registers.FR.matches_all(FR::RXFE::SET) {
419419
// immediately return in non-blocking mode.
420-
@@ -299,7 +299,12 @@
420+
@@ -293,7 +293,12 @@
421421
}
422422

423423
// Read one character.
@@ -431,7 +431,7 @@ diff -uNr 06_uart_chainloader/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs 07
431431

432432
// Update statistics.
433433
self.chars_read += 1;
434-
@@ -379,14 +384,14 @@
434+
@@ -373,14 +378,14 @@
435435
impl console::interface::Read for PL011Uart {
436436
fn read_char(&self) -> char {
437437
self.inner

07_timestamps/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

08_hw_debug_JTAG/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

09_privilege_level/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

10_virtual_mem_part1_identity_mapping/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

11_exceptions_part1_groundwork/src/bsp/device_driver/bcm/bcm2xxx_pl011_uart.rs

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -47,12 +47,6 @@ register_bitfields! {
4747
/// - If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
4848
TXFF OFFSET(5) NUMBITS(1) [],
4949

50-
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
51-
/// LCR_H Register.
52-
///
53-
/// If the FIFO is disabled, this bit is set when the receive holding register is empty. If
54-
/// the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
55-
5650
/// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the
5751
/// LCR_H Register.
5852
///

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