General purpose timer #31
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chipflow_digital_ip/base/gptimer.py
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| class GPTimer(Component): | ||
| class Ctrl(csr.Register, access="rw"): | ||
| """CTRL: [0]=EN, [1]=RST, [2]=AR, [3]=IRQ_EN""" |
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Could you make this documentation a bit more verbose as to the purpose of the bits?
chipflow_digital_ip/base/gptimer.py
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| # immediately clear our local pulse next cycle so it's one-hot | ||
| with m.If(mflag): | ||
| m.d.sync += mflag.eq(0) |
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Amaranth follows a last-assignment-first approach, so you can just do m.d.sync += mflag.eq(0) before the If statement where you set it to 1 and this will work just the same.
tests/test_gptimer.py
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| # clear the match bit | ||
| await self._write_reg(ctx, bus, self.REG_STATUS, 1, 1) | ||
| status2 = await self._read_reg(ctx, bus, self.REG_STATUS, 1) |
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it'd be fine just to reassign status here instead of calling this status2
chipflow_digital_ip/base/gptimer.py
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| self.bus.memory_map = self._bridge.bus.memory_map | ||
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| # Internal timer signals: | ||
| self._prescaler_cnt = Signal(8) |
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These don't need to be fields on self - they can just be created as signals in elaborate
chipflow_digital_ip/base/gptimer.py
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| # compare & auto-reload, set match-flag | ||
| with m.If((cnt_r == cmp_.val.data) & ctrl.en.data): | ||
| m.d.sync += mflag.eq(1) | ||
| with m.If(ctrl.ar.data): |
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is it intended if auto-reset isn't enabled, the counter will just roll around? (either way, this behaviour should be documented too)
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yeah the counter just keeps incrementing past the match value. i will document this functionality clearly
Created GPTimer and a testbench for it. Currently it works as intended and all tests pass.
For testing you can run "pytest tests/test_gptimer.py"