Plugin for checking the syntax of the Verilog language. Based on yosys.
Tested version: Micro 2.0.10; Yosys 2019.12.11
This plugin for work requires Yosys, install it in your system.
To install the plugin in micro editor, add to the configuration file:
micro ~/.config/micro/settings.json"pluginrepos": ["https://raw.githubusercontent.com/MuratovAS/micro-yosyslint/main/repo.json"],Installing the plugin in micro editor
micro -plugin install yosyslint- The plugin reports an ERROR in the code, but does not report a WARNING.
