[Draft][wip] Support composite vector register class for register allocation. #433
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niwinanto
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| def mCMs : AIE2PAcc1024RegisterClass<(add mCMm)>; | ||
| } // let SubRegIndices = [sub_512_lo, sub_512_hi], CoveredBySubRegs = 1 | ||
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| def eCML : AIE2PVector1024RegisterClass<(add cml0, cml1, cml2, cml3, cml4)>; |
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Curious, was this change also needed or just the dummy registers were enough?
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Maybe a description of the idea would be nice to help us to help. |
| @@ -33,8 +33,8 @@ def sub_512_hi : SubRegIndex<512, 512>; | |||
| def sub_512_acc_lo : SubRegIndex<512, 0>; | |||
| def sub_512_acc_hi : SubRegIndex<512, 512>; | |||
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| def sub_1024_acc_lo : SubRegIndex<1024, 0>; | |||
| def sub_1024_acc_hi : SubRegIndex<1024, 1024>; | |||
| def sub_1024_lo : SubRegIndex<1024, 0>; | |||
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I think this will lead to another problem. I heard once that we cannot reuse this for different register classes, maybe is related to the same problem that we have.
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Preliminary Core_StackSize results. |
…to mimic vector register hierarchy Subregister indices corresponds to vector and accumulator does not cover the co- rresponding sized registers and leads to undefined uses if we use same subregis- ter indices for both. Having separate subregister indices solves this problem. However, with this approach, we cannot allocate vector register for accumulator (or vice versa). The idea is to mimic the register composition hierarchy of vector for accumulator (only for smaller types, because 2048 does not matter) creating dummy 256-bit accumulators and reverting the separate subregister indices. Now, vector and accumulator register has same lane masks.
VEC/ACC/FIFO registers can be copied to each other and which can be used as an alternative to costly stack spill.
Upon spilling the composed register, we might need to select the spill/reload instruction based on the register allocated by the register allocator itself.
ItineraryRegPairs information is missing for the FIFO store registers(sf) with VMOV_alu_mv_mv_x and we might see wrongly scheduled code. Removed fifo store registers from the composed register class for the time being.
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VEC/ACC/FIFO registers can be copied to each other and which can be used as an alternative to costly stack spill. However, the problem of having a composite register class is, sub-register indices corresponds to vector and accumulator does not cover the corresponding sized registers and leads to undefined uses if we use same sub-register indices for both.
The idea is to mimic the register composition hierarchy of vector for accumulator (only for smaller types, because 2048 does not matter) creating dummy 256-bit accumulators and reverting the separate sub-register indices. Now, vector and accumulator register has same lane masks.