projects/cn0577: Add build parameters, update IP GUI

library/axi_ltc2387/axi_ltc2387.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -52,7 +52,7 @@ module axi_ltc2387 #(
   parameter OUT_RES = 32, // 32-bit for ADC_RES=18 or 16-bit for ADC_RES=16
   parameter TWOLANES = 1
 ) (
-  input                     delay_clk,
+  input                    delay_clk,
 
   // adc interface
 
@@ -159,7 +159,7 @@ module axi_ltc2387 #(
     .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
     .IO_DELAY_GROUP (IO_DELAY_GROUP),
     .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
-    .RESOLUTION (ADC_RES),
+    .ADC_RES (ADC_RES),
     .IODELAY_CTRL (IODELAY_CTRL),
     .TWOLANES (TWOLANES)
   ) i_if (

library/axi_ltc2387/axi_ltc2387_channel.v

@@ -101,7 +101,13 @@ module axi_ltc2387_channel #(
 
   assign adc_pn_err_s = adc_pn_err;
 
-  // expected pattern
+  // expected patterns:
+  // 18-bit, one-lane: 10 1000 0001 1111 1100
+  // 16-bit, one-lane: 10 1000 0001 1111 11
+  // 18-bit, two-lane: 11 0011 0000 1111 1100
+  // 16-bit, one-lane: 11 0011 0000 1111 11
+  // basically, the 16-bit variant doesn't have the LSBs 00
+  // so we can sum this up as the 16-bit expected pattern + 2 zeroes for the 18-bit one
 
   generate
     if (TWOLANES == 1) begin

library/axi_ltc2387/axi_ltc2387_if.v

@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -44,7 +44,7 @@ module axi_ltc2387_if #(
   parameter IODELAY_CTRL = 1,
   parameter DELAY_REFCLK_FREQUENCY = 200,
   parameter TWOLANES = 1,    // 0 for one-lane, 1 for two lanes
-  parameter RESOLUTION = 18  // 16 or 18 bits
+  parameter ADC_RES = 18  // 16 or 18 bits
 ) (
 
   // delay interface
@@ -68,12 +68,12 @@ module axi_ltc2387_if #(
   input             db_p,
   input             db_n,
 
-  output reg                  adc_valid,
-  output reg [RESOLUTION-1:0] adc_data
+  output reg               adc_valid,
+  output reg [ADC_RES-1:0] adc_data
 );
 
-  localparam ONE_L_WIDTH = (RESOLUTION == 18) ? 9 : 8;
-  localparam TWO_L_WIDTH = (RESOLUTION == 18) ? 5 : 4;
+  localparam ONE_L_WIDTH = (ADC_RES == 18) ? 9 : 8;
+  localparam TWO_L_WIDTH = (ADC_RES == 18) ? 5 : 4;
   localparam WIDTH = (TWOLANES == 0) ? ONE_L_WIDTH : TWO_L_WIDTH;
 
   // internal wires
@@ -100,7 +100,7 @@ module axi_ltc2387_if #(
     adc_valid <= 1'b0;
     clk_gate_d <= {clk_gate_d[1:0], clk_gate};
     if (clk_gate_d[1] == 1'b1 && clk_gate_d[0] == 1'b0) begin
-      if (RESOLUTION == 18) begin
+      if (ADC_RES == 18) begin
         adc_data <= adc_data_int;
         adc_valid <= 1'b1;
       end else begin
@@ -113,8 +113,13 @@ module axi_ltc2387_if #(
   always @(posedge dco) begin
     adc_data_da_p <= {adc_data_da_p[WIDTH-1:0], da_p_int_s};
     adc_data_da_n <= {adc_data_da_n[WIDTH-1:0], da_n_int_s};
-    adc_data_db_p <= {adc_data_db_p[WIDTH-1:0], db_p_int_s};
-    adc_data_db_n <= {adc_data_db_n[WIDTH-1:0], db_n_int_s};
+    if (TWOLANES) begin
+      adc_data_db_p <= {adc_data_db_p[WIDTH-1:0], db_p_int_s};
+      adc_data_db_n <= {adc_data_db_n[WIDTH-1:0], db_n_int_s};
+    end else begin
+      adc_data_db_p <= 'd0;
+      adc_data_db_n <= 'd0;
+    end
   end
 
   // bits rearrangement
@@ -139,7 +144,7 @@ module axi_ltc2387_if #(
     assign adc_data_int[1] = da_p_int_s;
     assign adc_data_int[0] = da_n_int_s;
   end else begin
-    if (RESOLUTION == 18) begin
+    if (ADC_RES == 18) begin
       assign adc_data_int[17] = adc_data_da_p[3];
       assign adc_data_int[16] = adc_data_db_p[3];
       assign adc_data_int[15] = adc_data_da_n[3];
@@ -200,25 +205,34 @@ module axi_ltc2387_if #(
     .delay_rst (delay_rst),
     .delay_locked (delay_locked));
 
-  ad_data_in #(
-    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
-    .IDDR_CLK_EDGE ("OPPOSITE_EDGE"),
-    .IODELAY_CTRL (0),
-    .IODELAY_GROUP (IO_DELAY_GROUP),
-    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
-  ) i_rx_db (
-    .rx_clk (dco),
-    .rx_data_in_p (db_p),
-    .rx_data_in_n (db_n),
-    .rx_data_p (db_p_int_s),
-    .rx_data_n (db_n_int_s),
-    .up_clk (up_clk),
-    .up_dld (up_dld[1]),
-    .up_dwdata (up_dwdata[9:5]),
-    .up_drdata (up_drdata[9:5]),
-    .delay_clk (delay_clk),
-    .delay_rst (delay_rst),
-    .delay_locked ());
+  // instantiate only if TWOLANES
+  if (TWOLANES) begin
+    ad_data_in #(
+      .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+      .IDDR_CLK_EDGE ("OPPOSITE_EDGE"),
+      .IODELAY_CTRL (0),
+      .IODELAY_GROUP (IO_DELAY_GROUP),
+      .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY)
+    ) i_rx_db (
+      .rx_clk (dco),
+      .rx_data_in_p (db_p),
+      .rx_data_in_n (db_n),
+      .rx_data_p (db_p_int_s),
+      .rx_data_n (db_n_int_s),
+      .up_clk (up_clk),
+      .up_dld (up_dld[1]),
+      .up_dwdata (up_dwdata[9:5]),
+      .up_drdata (up_drdata[9:5]),
+      .delay_clk (delay_clk),
+      .delay_rst (delay_rst),
+      .delay_locked ());
+  end else begin
+    // when in one-lane mode, tie them to 0,
+    // otherwise the input pin of input buffer
+    // will have an illegal connection to logic constant value
+    assign db_p_int_s = 1'b0;
+    assign db_n_int_s = 1'b0;
+  end
 
   // clock
 

library/axi_ltc2387/axi_ltc2387_ip.tcl

@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -31,68 +31,72 @@ adi_ip_files axi_ltc2387 [list \
 
 adi_ip_properties axi_ltc2387
 
-set cc [ipx::current_core]
-set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
+ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dco_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
+ipx::infer_bus_interface dco_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
 
-ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 $cc
-ipx::infer_bus_interface dco_p xilinx.com:signal:clock_rtl:1.0 $cc
-ipx::infer_bus_interface dco_n xilinx.com:signal:clock_rtl:1.0 $cc
+set cc [ipx::current_core]
 
-ipgui::add_static_text -name {Warning} -component $cc -parent $page0 -text {In one-lane mode, only 18-bit resolution is supported!
-Output data width (OUT_RES) depends on ADC_RES!}
+set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
 
 ipx::add_user_parameter ADC_RES $cc
 set_property value_resolve_type user [ipx::get_user_parameters ADC_RES -of_objects $cc]
 ipgui::add_param -name "ADC_RES" -component $cc -parent $page0
 set_property -dict [list \
-  "display_name" "ADC_RES" \
-  "layout" "horizontal" \
-  "tooltip" "ADC resolution" \
+  "display_name" "ADC resolution" \
+  "tooltip" "ADC_RES" \
   "widget" "radioGroup" \
+  "layout" "horizontal" \
 ] [ipgui::get_guiparamspec -name "ADC_RES" -component $cc]
 
 set_property -dict [list \
-  "value" "18" \
   "value_format" "long" \
   "value_validation_type" "list" \
-  "value_validation_list" "18 16" \
+  "value_validation_list" "16 18" \
 ] [ipx::get_user_parameters ADC_RES -of_objects $cc]
 
-# OUT_RES depends on the value of ADC_RES, and is set in the project
 ipx::add_user_parameter OUT_RES $cc
 set_property value_resolve_type user [ipx::get_user_parameters OUT_RES -of_objects $cc]
 ipgui::add_param -name "OUT_RES" -component $cc -parent $page0
 set_property -dict [list \
-  "display_name" "OUT_RES" \
-  "layout" "horizontal" \
-  "tooltip" "Output data width" \
+  "display_name" "Output data width" \
+  "tooltip" "OUT_RES" \
   "widget" "radioGroup" \
+  "layout" "horizontal" \
 ] [ipgui::get_guiparamspec -name "OUT_RES" -component $cc]
 
 set_property -dict [list \
-  "value" "32" \
   "value_format" "long" \
   "value_validation_type" "list" \
-  "value_validation_list" "32 16" \
+  "value_validation_list" "16 32" \
 ] [ipx::get_user_parameters OUT_RES -of_objects $cc]
 
 ipx::add_user_parameter TWOLANES $cc
 set_property value_resolve_type user [ipx::get_user_parameters TWOLANES -of_objects $cc]
 ipgui::add_param -name "TWOLANES" -component $cc -parent $page0
 set_property -dict [list \
-  "display_name" "TWOLANES" \
-  "layout" "horizontal" \
-  "tooltip" "Two-lane mode (1) or one-lane mode (0)" \
+  "display_name" "Lane mode" \
+  "tooltip" "TWOLANES" \
   "widget" "radioGroup" \
+  "layout" "horizontal" \
 ] [ipgui::get_guiparamspec -name "TWOLANES" -component $cc]
 
 set_property -dict [list \
-  "value" "1" \
   "value_format" "long" \
   "value_validation_type" "list" \
-  "value_validation_list" "1 0" \
+  "value_validation_list" "0 1" \
 ] [ipx::get_user_parameters TWOLANES -of_objects $cc]
 
+# if TWOLANES=0, disable and tie to GND, ports db_p, db_n
+adi_set_ports_dependency "db_p" \
+  "(spirit:decode(id('MODELPARAM_VALUE.TWOLANES')) == 1)"
+adi_set_ports_dependency "db_n" \
+  "(spirit:decode(id('MODELPARAM_VALUE.TWOLANES')) == 1)"
+
+set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects $cc]
+
+#adi_add_auto_fpga_spec_params
+
 ipx::create_xgui_files $cc
 ipx::update_checksums $cc
 ipx::save_core $cc

projects/cn0577/README.md

@@ -1,6 +1,10 @@
 # CN0577 HDL Project
 
-- Evaluation board product page: [EVAL-CN0577](https://www.analog.com/cn0577)
+- Evaluation board product page:
+  - [EVAL-CN0577](https://www.analog.com/cn0577)
+  - [EVAL-ADAQ23878](https://analog.com/eval-adaq23878)
+  - [EVAL-ADAQ23876](https://analog.com/eval-adaq23876)
+  - [EVAL-ADAQ23875](https://analog.com/eval-adaq23875)
 - System documentation: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577 
 - HDL project documentation: http://analogdevicesinc.github.io/hdl/projects/cn0577/index.html
 - Evaluation board VADJ: 2.5V
@@ -9,8 +13,11 @@
 
 | Part name                               | Description                                               |
 |-----------------------------------------|-----------------------------------------------------------|
-| [ADAQ23876](https://www.analog.com/ADAQ23876) | 16-Bit, 15 MSPS, μModule Data Acquisition Solution |
 | [LTC2387-18](https://www.analog.com/LTC2387-18) | 18-Bit, 15 MSPS, SAR ADC |
+| [LTC2387-16](https://www.analog.com/LTC2387-16) | 16-Bit, 15 MSPS, SAR ADC |
+| [ADAQ23878](https://www.analog.com/ADAQ23878) | 18-Bit, 15 MSPS, μModule Data Acquisition Solution |
+| [ADAQ23876](https://www.analog.com/ADAQ23876) | 16-Bit, 15 MSPS, μModule Data Acquisition Solution |
+| [ADAQ23875](https://www.analog.com/ADAQ23875) | 16-Bit, 15 MSPS, μModule Data Acquisition Solution |
 
 ## Building the project
 

projects/cn0577/common/cn0577_bd.tcl

@@ -1,9 +1,20 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-# ltc2387
+# env params
+
+set TWOLANES $ad_project_params(TWOLANES);  # two-lane mode (1) or one-lane mode (0); default two-lane
+set ADC_RES $ad_project_params(ADC_RES);    # ADC resolution; default 18 bits
+set OUT_RES [expr {$ADC_RES == 16 ? 16 : 32}]
+set CLK_GATE_WIDTH [expr {($TWOLANES == 0 && $ADC_RES == 18) ? 9 : \
+                          ($TWOLANES == 0 && $ADC_RES == 16) ? 8 : \
+                          ($TWOLANES == 1 && $ADC_RES == 18) ? 5 : \
+                          4}]
+
+# ltc2387 i/o
+
 create_bd_port -dir I ref_clk
 create_bd_port -dir O sampling_clk
 create_bd_port -dir I dco_p
@@ -18,9 +29,9 @@ create_bd_port -dir O clk_gate
 # adc peripheral
 
 ad_ip_instance axi_ltc2387 axi_ltc2387
-ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES 18
-ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES 32
-ad_ip_parameter axi_ltc2387 CONFIG.TWOLANES $two_lanes
+ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES $ADC_RES
+ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES $OUT_RES
+ad_ip_parameter axi_ltc2387 CONFIG.TWOLANES $TWOLANES
 ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 27
 
 # axi pwm gen
@@ -29,7 +40,7 @@ ad_ip_instance axi_pwm_gen axi_pwm_gen
 ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 2
 ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 1
 ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 8
-ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_WIDTH 5
+ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_WIDTH $CLK_GATE_WIDTH
 ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_PERIOD 8
 ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_OFFSET 0
 
@@ -43,7 +54,7 @@ ad_ip_parameter axi_ltc2387_dma CONFIG.SYNC_TRANSFER_START 0
 ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_SRC 0
 ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_DEST 0
 ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_2D_TRANSFER 0
-ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_SRC 32
+ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_SRC $OUT_RES
 ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_DEST 64
 
 # connections
@@ -58,8 +69,11 @@ ad_connect dco_p      axi_ltc2387/dco_p
 ad_connect dco_n      axi_ltc2387/dco_n
 ad_connect da_p       axi_ltc2387/da_p
 ad_connect da_n       axi_ltc2387/da_n
-ad_connect db_p       axi_ltc2387/db_p
-ad_connect db_n       axi_ltc2387/db_n
+
+if {$TWOLANES == "1"} {
+  ad_connect db_p       axi_ltc2387/db_p
+  ad_connect db_n       axi_ltc2387/db_n
+}
 
 ad_connect ref_clk                axi_ltc2387_dma/fifo_wr_clk
 ad_connect axi_ltc2387/adc_valid  axi_ltc2387_dma/fifo_wr_en