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@caosjr caosjr commented Sep 17, 2025

ROOM and LEVEL signals are incorrect when there is an imbalance between the size of the input and output and TKEEP_EN == 1. This is fixed by inserting two counters, which are better for timing than performing a sum reduce ROOM and LEVEL of the internal symmetrical FIFOs.
This PR has to be merged after #1914

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)
  • Documentation

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
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  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

@caosjr caosjr requested a review from LBFFilho September 17, 2025 14:17
@caosjr caosjr force-pushed the fix_fifo_asym_room_level branch from 0cb347f to 71dc96f Compare September 17, 2025 14:25
.in_clk (m_axis_aclk),
.in_event (m_axis_ready & m_axis_valid),
.out_clk (s_axis_aclk),
.out_event (sdi_output_read_sync));
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sdi_output_read_sync I suggest renaming this

@caosjr caosjr force-pushed the fix_fifo_asym_room_level branch from 71dc96f to d5a3007 Compare September 23, 2025 13:28
LBFFilho and others added 3 commits September 24, 2025 00:17
Fix a bug where m_axis_valid waits on m_axis_ready to be asserted a few times in
order to skip over data for which tkeep was all zeroes. This was a violation of
the AXI Streaming protocol.

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Fix tvalid low when tlast is present.

Before this commit, util_axis_fifo would suppress all transfers with tkeep=0,
even if tlast was asserted. This commit makes it so transfers with tlast
asserted are preserved.

The AXI-Streaming spec allows us to suppress transfers for which all tkeep bits
are 0 (all bytes are null bytes), but only in the case when tlast=0 as well.
Transfers where tlast is asserted can't be suppressed even when all bytes are
null.

Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
ROOM and LEVEL signals are incorrect when there is an imbalance
between the size of the input and output and TKEEP_EN == 1. This
commit fixes this issue by inserting two counters, which are
better for timing than performing a sum reduce ROOM and LEVEL
of the internal symmetrical FIFOs

Signed-off-by: Carlos Souza <carlos.souza@analog.com>
@caosjr caosjr force-pushed the fix_fifo_asym_room_level branch from d5a3007 to b4e690a Compare September 24, 2025 19:04
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2 participants