Computer Architecture Projects

Contents

• 4 bit MIPS Processor
• Floating Point Adder
• 4 bit ALU (Arithmetic Logic Unit)

4 bit MIPS Processor

Implemented a single-cycle 4-bit MIPS processor implementation that can execute a subset of MIPS instructions. The processor follows the classic five-stage datapath design. The main components include:

1. Program Counter (PC) and Instruction Fetch

• 8-bit D Flip-Flop: Stores the current program counter
• Instruction Memory: ROM containing 16-bit instructions
• PC Logic: Handles sequential execution and jumps
• Multiplexer: Selects between PC+1 (sequential) and jump address

2. Control Unit

• Input: 4-bit opcode from instruction[15:12]
• ROM-based: Uses a lookup table to generate control signals
• Outputs: 12 control signals including:
  • RegDst: Register destination selection
  • RegWrite: Enable register writing
  • ALUSrc: ALU source selection
  • MemRead/MemWrite: Memory operation controls
  • MemtoReg: Memory to register data selection
  • Branch controls (beq, bneq)
  • Jump control
  • ALUop: 3-bit ALU operation code

3. Register File

• 5 Registers: $t0, $t1, $t2, $t3, $t4 (4-bit each)
• Dual Read Ports: Can read two registers simultaneously
• Single Write Port: Writes to one register per cycle
• Clock-enabled Writing: Only writes when RegWrite is asserted

4. ALU (Arithmetic Logic Unit)

• 4-bit inputs: A and B
• 8 Operations: Based on 3-bit ALUop control
  • Addition, Subtraction
  • Logical AND, OR, NOR
  • Shift operations (left/right)
• Zero Flag: Used for branch instructions

5. Data Memory

• RAM: 4-bit address, 4-bit data width
• Separate Read/Write: Controlled by MemRead/MemWrite signals
• Clock-synchronized: Memory operations occur on clock edge

6. 8-bit Adder/Subtractor

• PC Arithmetic: Handles PC+1 for sequential execution
• Branch Target: Calculates branch addresses
• Mode Selection: Can add or subtract based on control

Instruction Formats Supported

R-type Instructions (Register-Register)

[15:12] [11:8] [7:4] [3:0]
Opcode  Src1   Src2  Dest

Examples: add, sub, and, or, nor

I-type Instructions (Immediate)

[15:12] [11:8] [7:4] [3:0]
Opcode  Src1   Dest  Immediate/Address

Examples: addi, andi, ori, lw, sw, beq, bneq

S-type Instructions (Shift)

[15:12] [11:8] [7:4] [3:0]
Opcode  Src1   Dest  Shift_Amount

Examples: sll, srl

J-type Instructions (Jump)

[15:12] [11:4] [3:0]
Opcode  Jump_Address  0000

Example: j (jump)

Datapath Flow

1. Instruction Fetch: PC → Instruction Memory → 16-bit instruction
2. Decode: Instruction fields split and sent to respective components
3. Register Read: Register file outputs source register values
4. Execute: ALU performs operation based on ALUop
5. Memory Access: Load/Store operations access data memory
6. Write Back: Results written to destination register

Control Signal Generation

The control unit uses a ROM lookup table where:

• Address: 4-bit opcode
• Data: 12-bit control word containing all necessary control signals

Multiplexers for Data Path Selection

• ALU Source: Choose between register or immediate value
• Register Destination: R-type vs I-type destination selection
• Write Data: ALU result vs Memory data vs PC+1
• PC Source: Sequential vs Jump vs Branch address

Branch Logic

• Zero Detection: ALU zero flag for beq/bneq
• Branch Address: PC + offset calculation
• Branch Decision: AND gate combines branch control with condition

Memory Interface

• Instruction Memory: Read-only, addressed by PC
• Data Memory: Read/Write, addressed by ALU result
• Separate Address Spaces: Harvard architecture style

Instruction Set Architecture

The processor implements 16 different instructions (4-bit opcode):

• Arithmetic: add, sub, addi, subi
• Logic: and, or, nor, andi, ori
• Shift: sll, srl
• Memory: lw, sw
• Control: beq, bneq, j

Circuit diagram:

How to use

Write a valid MIPS assembly code and compile the code with MIPS-assembler. Now open the MIPS-simulator with logisim 2.7.1 Then open the machine.txt file (generated after runnig the C++ code) from the instruction memory.

MIPS instruction formats:

• R-type:

Opcode	Src Reg 1	Src Reg 2	Dst Reg
4-bits	4-bits	4-bits	4-bits

• S-type:

Opcode	Src Reg 1	Dst Reg	Shamt
4-bits	4-bits	4-bits	4-bits

• I-type:

Opcode	Src Reg 1	Src Reg 2/Dst Reg	Addr./Immdt
4-bits	4-bits	4-bits	4-bits

• J-type:

Opcode	Target Jump Address		0
4-bits	8-bits		4-bits

Instruction set:

Instruction Opcode	Instruction	MIPS Instruction Format	Instruction Type
0000	sub	R	Arithmetic
0001	ori	I	Logic
0010	bneq	I	Control
0011	addi	I	Arithmetic
0100	beq	I	Control
0101	or	R	Logic
0110	sw	I	Memory
0111	srl	S	Logic
1000	and	R	Logic
1001	andi	I	Logic
1010	lw	I	Memory
1011	add	R	Arithmetic
1100	sll	S	Logic
1101	subi	I	Arithmetic
1110	j	J	Control
1111	nor	R	Logic

Floating Point Adder

The adder takes two 32 bit floating point numbers and adds them together. The numbers are represented in the following format:

Sign	Exponent	Fraction
1 bit	10 bits	21 bits (Lowest bits)

The numbers are in normalized form. There are two flags U (underflow) and O (overflow) which are set if the result is too small or too large to be represented in the format.

Flow chart:

Circuit diagram:

What individual components do:

• Sign check: Checks if a 32 floating point number is positive, negative or the exponent is zero. If the number is positive then the output is the same as input. If the number is negative then it outputs the two's complement of the input. And if the exponent is zero then the output is zero.
• Normalizer: Normalizes a floating point number. But if the number is overflowed or under flowed while trying to normalize then the appropriate flags are set.
• Rounder: Rounds the 32 bit significant to 21 bits.

4 bit ALU

This ALU contains:

• Two 4 bit inputs A and B
• Three select bits S₂, S₁, S₀ as ALU opcodes
• One 4 bit output
• Four flags: Z (Zero), C (Carry), O (Overflow), N (Negative)

Implemented functions and opcodes:

ALU opcodes			Functions
S2	S1	S0 (Cin)
0	0	0	Transfer A
0	0	1	Increment A
0	1	X	AND
1	0	0	Add
1	0	1	Add with carry
1	1	X	OR

Truth table:

ALU opcodes			Required outputs	Adder inputs			Functions
S2	S1	S0 (Cin)		Xi	Yi	Zi
0	0	0	A	Ai	0	Ci	Transfer A
0	0	1	A + 1				Increment A
0	1	0	A ^ B	AiBi	0	0	AND
0	1	1
1	0	0	A + B	Ai	Bi	Ci	Add
1	0	1	A + B + 1				Add with carry
1	1	0	A OR B	AiBi'	Bi	0	OR
1	1	1

Simplified inputs to individual full adders:

X_i = A(S₁' + S₂ XOR B)

Y_i = S₂B

Z_i = S₁'C_i

Circuit diagram:

Group Members:

• Anup Bhowmik
• Showvik Biswas
• Fardin Anam Aungon
• Kazi Ababil Azam
• Muhammad Ehsanul Kader