arcv: correct mode for widening XARCV instructions

gcc/testsuite/gcc.target/riscv/arcv-bitrev-bitrev-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_bitrev } */
 /* { dg-options "-march=rv32im_xarcvbitrev -mabi=ilp32" } */
 
 #include <stddef.h>

gcc/testsuite/gcc.target/riscv/arcv-bitstream-bspeek-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_bitstream } */
 /* { dg-options "-march=rv32im_xarcvbitstream -mabi=ilp32" } */
 
 #include <stddef.h>

gcc/testsuite/gcc.target/riscv/arcv-bitstream-bspop-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_bitstream } */
 /* { dg-options "-march=rv32im_xarcvbitstream -mabi=ilp32" } */
 
 #include <stddef.h>

gcc/testsuite/gcc.target/riscv/arcv-bitstream-bspush-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_bitstream } */
 /* { dg-options "-march=rv32im_xarcvbitstream -mabi=ilp32" } */
 
 #include <stddef.h>

gcc/testsuite/gcc.target/riscv/arcv-mxmb-vqmxm4_vv-compile-1.c

@@ -1,13 +1,27 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_mxmb } */
-/* { dg-options "-march=rv32im_xarcvmxmb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32im_xarcvmxmb -mabi=ilp32 -O2" } */
 
 #include <stddef.h>
 #include <riscv_vector.h>
 
+
+/*
+** test_vqmxm4_vv_i8:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm4\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])
+**  ret
+*/
 vint32m4_t test_vqmxm4_vv_i8 (vint32m4_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm4_vv_i32m4 (vd, vs1, vs2, vl); }
+
+/*
+** test_vqmxm4_vv_i8_m:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm4\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])\.t
+**  ret
+*/
 vint32m4_t test_vqmxm4_vv_i8_m (vbool8_t mask, vint32m4_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm4_vv_i32m4_m (mask, vd, vs1, vs2, vl); }
 
-/* { dg-final { scan-assembler-times "arcv\\.vqmxm4\\.vv" 2 } } */
+/* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/arcv-mxmb-vqmxm4su_vv-compile-1.c

@@ -1,13 +1,27 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_mxmb } */
-/* { dg-options "-march=rv32im_xarcvmxmb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32im_xarcvmxmb -mabi=ilp32 -O2" } */
 
 #include <stddef.h>
 #include <riscv_vector.h>
 
+
+/*
+** test_vqmxm4su_vv_i8:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm4su\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])
+**  ret
+*/
 vint32m4_t test_vqmxm4su_vv_i8 (vint32m4_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm4su_vv_i32m4 (vd, vs1, vs2, vl); }
+
+/*
+** test_vqmxm4su_vv_i8_m:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm4su\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])\.t
+**  ret
+*/
 vint32m4_t test_vqmxm4su_vv_i8_m (vbool8_t mask, vint32m4_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm4su_vv_i32m4_m (mask, vd, vs1, vs2, vl); }
 
-/* { dg-final { scan-assembler-times "arcv\\.vqmxm4su\\.vv" 2 } } */
+/* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/arcv-mxmb-vqmxm4u_vv-compile-1.c

@@ -1,13 +1,27 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_mxmb } */
-/* { dg-options "-march=rv32im_xarcvmxmb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32im_xarcvmxmb -mabi=ilp32 -O2" } */
 
 #include <stddef.h>
 #include <riscv_vector.h>
 
+
+/*
+** test_vqmxm4u_vv_u8:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm4u\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])
+**  ret
+*/
 vuint32m4_t test_vqmxm4u_vv_u8 (vuint32m4_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm4u_vv_u32m4 (vd, vs1, vs2, vl); }
+
+/*
+** test_vqmxm4u_vv_u8_m:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm4u\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])\.t
+**  ret
+*/
 vuint32m4_t test_vqmxm4u_vv_u8_m (vbool8_t mask, vuint32m4_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm4u_vv_u32m4_m (mask, vd, vs1, vs2, vl); }
 
-/* { dg-final { scan-assembler-times "arcv\\.vqmxm4u\\.vv" 2 } } */
+/* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/arcv-mxmc-vqmxm8_vv-compile-1.c

@@ -1,13 +1,27 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_mxmc } */
-/* { dg-options "-march=rv32im_xarcvmxmc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32im_xarcvmxmc -mabi=ilp32 -O2" } */
 
 #include <stddef.h>
 #include <riscv_vector.h>
 
+
+/*
+** test_vqmxm8_vv_i8:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm8\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])
+**  ret
+*/
 vint32m4_t test_vqmxm8_vv_i8 (vint32m4_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm8_vv_i32m4 (vd, vs1, vs2, vl); }
+
+/*
+** test_vqmxm8_vv_i8_m:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm8\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])\.t
+**  ret
+*/
 vint32m4_t test_vqmxm8_vv_i8_m (vbool8_t mask, vint32m4_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm8_vv_i32m4_m (mask, vd, vs1, vs2, vl); }
 
-/* { dg-final { scan-assembler-times "arcv\\.vqmxm8\\.vv" 2 } } */
+/* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/arcv-mxmc-vqmxm8su_vv-compile-1.c

@@ -1,13 +1,27 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_mxmc } */
-/* { dg-options "-march=rv32im_xarcvmxmc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32im_xarcvmxmc -mabi=ilp32 -O2" } */
 
 #include <stddef.h>
 #include <riscv_vector.h>
 
+
+/*
+** test_vqmxm8su_vv_i8:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm8su\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])
+**  ret
+*/
 vint32m4_t test_vqmxm8su_vv_i8 (vint32m4_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm8su_vv_i32m4 (vd, vs1, vs2, vl); }
+
+/*
+** test_vqmxm8su_vv_i8_m:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm8su\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])\.t
+**  ret
+*/
 vint32m4_t test_vqmxm8su_vv_i8_m (vbool8_t mask, vint32m4_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm8su_vv_i32m4_m (mask, vd, vs1, vs2, vl); }
 
-/* { dg-final { scan-assembler-times "arcv\\.vqmxm8su\\.vv" 2 } } */
+/* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/arcv-mxmc-vqmxm8u_vv-compile-1.c

@@ -1,13 +1,27 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_mxmc } */
-/* { dg-options "-march=rv32im_xarcvmxmc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32im_xarcvmxmc -mabi=ilp32 -O2" } */
 
 #include <stddef.h>
 #include <riscv_vector.h>
 
+
+/*
+** test_vqmxm8u_vv_u8:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm8u\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])
+**  ret
+*/
 vuint32m4_t test_vqmxm8u_vv_u8 (vuint32m4_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm8u_vv_u32m4 (vd, vs1, vs2, vl); }
+
+/*
+** test_vqmxm8u_vv_u8_m:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm8u\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])\.t
+**  ret
+*/
 vuint32m4_t test_vqmxm8u_vv_u8_m (vbool8_t mask, vuint32m4_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm8u_vv_u32m4_m (mask, vd, vs1, vs2, vl); }
 
-/* { dg-final { scan-assembler-times "arcv\\.vqmxm8u\\.vv" 2 } } */
+/* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/arcv-mxmd-vqmxm16_vv-compile-1.c

@@ -1,13 +1,27 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_mxmd } */
-/* { dg-options "-march=rv32im_xarcvmxmd -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32im_xarcvmxmd -mabi=ilp32 -O2" } */
 
 #include <stddef.h>
 #include <riscv_vector.h>
 
+
+/*
+** test_vqmxm16_vv_i8:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm16\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])
+**  ret
+*/
 vint32m4_t test_vqmxm16_vv_i8 (vint32m4_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm16_vv_i32m4 (vd, vs1, vs2, vl); }
+
+/*
+** test_vqmxm16_vv_i8_m:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm16\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])\.t
+**  ret
+*/
 vint32m4_t test_vqmxm16_vv_i8_m (vbool8_t mask, vint32m4_t vd, vint8m1_t vs1, vint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm16_vv_i32m4_m (mask, vd, vs1, vs2, vl); }
 
-/* { dg-final { scan-assembler-times "arcv\\.vqmxm16\\.vv" 2 } } */
+/* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/arcv-mxmd-vqmxm16su_vv-compile-1.c

@@ -1,13 +1,27 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_mxmd } */
-/* { dg-options "-march=rv32im_xarcvmxmd -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32im_xarcvmxmd -mabi=ilp32 -O2" } */
 
 #include <stddef.h>
 #include <riscv_vector.h>
 
+
+/*
+** test_vqmxm16su_vv_i8:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm16su\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])
+**  ret
+*/
 vint32m4_t test_vqmxm16su_vv_i8 (vint32m4_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm16su_vv_i32m4 (vd, vs1, vs2, vl); }
+
+/*
+** test_vqmxm16su_vv_i8_m:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm16su\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])\.t
+**  ret
+*/
 vint32m4_t test_vqmxm16su_vv_i8_m (vbool8_t mask, vint32m4_t vd, vint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm16su_vv_i32m4_m (mask, vd, vs1, vs2, vl); }
 
-/* { dg-final { scan-assembler-times "arcv\\.vqmxm16su\\.vv" 2 } } */
+/* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/arcv-mxmd-vqmxm16u_vv-compile-1.c

@@ -1,13 +1,27 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_mxmd } */
-/* { dg-options "-march=rv32im_xarcvmxmd -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O3" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-options "-march=rv32im_xarcvmxmd -mabi=ilp32 -O2" } */
 
 #include <stddef.h>
 #include <riscv_vector.h>
 
+
+/*
+** test_vqmxm16u_vv_u8:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm16u\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])
+**  ret
+*/
 vuint32m4_t test_vqmxm16u_vv_u8 (vuint32m4_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm16u_vv_u32m4 (vd, vs1, vs2, vl); }
+
+/*
+** test_vqmxm16u_vv_u8_m:
+**  vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,m1,\s*t[au],\s*m[au]
+**  arcv\.vqmxm16u\.vv\s+(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1]),\s*(?:v[0-9]|v[1-2][0-9]|[a-x0-9]+[0-1])\.t
+**  ret
+*/
 vuint32m4_t test_vqmxm16u_vv_u8_m (vbool8_t mask, vuint32m4_t vd, vuint8m1_t vs1, vuint8m1_t vs2, size_t vl) {
   return __riscv_arcv_vqmxm16u_vv_u32m4_m (mask, vd, vs1, vs2, vl); }
 
-/* { dg-final { scan-assembler-times "arcv\\.vqmxm16u\\.vv" 2 } } */
+/* { dg-final { check-function-bodies "**" "" } } */

gcc/testsuite/gcc.target/riscv/arcv-udsp-bitrev-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vadd-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vnclip-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vsadd-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vscjmul-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vscmul-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vsll-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vsra-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vssub-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vsub-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vwmul-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vwscjmul-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int

gcc/testsuite/gcc.target/riscv/arcv-udsp-vwscjrdot-compile-1.c

@@ -1,5 +1,4 @@
 /* { dg-do compile } */
-/* { dg-require-effective-target arcv_udsp } */
 /* { dg-options "-march=rv32i_xarcvudsp -mabi=ilp32" } */
 
 int