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AMDGPU: Allow readonly features to be written to IR when there is no target #148141

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Merged
merged 9 commits into from
Jul 29, 2025
+22 −3
Merged

AMDGPU: Allow readonly features to be written to IR when there is no target #148141

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c9cf987
AMDGPU: Remove "gws" from the “read-only” target feature list
changpeng Jul 11, 2025
5beb2e8
AMDGPU: Remove "gws" from the “read-only” target feature list
changpeng Jul 11, 2025
d78dfd9
AMDGPU: Remove "gws" from the “read-only” target feature list
changpeng Jul 11, 2025
de11611
Merge branch 'llvm:main' into readonly
changpeng Jul 15, 2025
afeec4b
Merge branch 'llvm:main' into readonly
changpeng Jul 16, 2025
532226f
Merge branch 'llvm:main' into readonly
changpeng Jul 18, 2025
57ea48f
Merge branch 'llvm:main' into readonly
changpeng Jul 21, 2025
56aa23d
AMDGPU: Mark features as read-only only when target supports them
changpeng Jul 21, 2025
870f9a9
AMDGPU: Allow readonly features to be written to IR when there is no …
changpeng Jul 22, 2025
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7 changes: 5 additions & 2 deletions clang/lib/Basic/Targets/AMDGPU.cpp
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Expand Up @@ -266,8 +266,11 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple &Triple,

MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
CUMode = !(GPUFeatures & llvm::AMDGPU::FEATURE_WGP);
for (auto F : {"image-insts", "gws", "vmem-to-lds-load-insts"})
ReadOnlyFeatures.insert(F);

for (auto F : {"image-insts", "gws", "vmem-to-lds-load-insts"}) {
if (GPUKind != llvm::AMDGPU::GK_NONE)
ReadOnlyFeatures.insert(F);
}
HalfArgsAndReturns = true;
}

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2 changes: 1 addition & 1 deletion clang/test/CodeGenOpenCL/amdgpu-features-readonly.cl
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@@ -1,4 +1,4 @@
// RUN: %clang_cc1 -triple amdgcn -target-feature +gws -o /dev/null %s 2>&1 \
// RUN: %clang_cc1 -triple amdgcn -target-cpu gfx942 -target-feature +gws -o /dev/null %s 2>&1 \
// RUN: | FileCheck --check-prefix=GWS %s

// GWS: warning: feature flag '+gws' is ignored since the feature is read only [-Winvalid-command-line-argument]
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16 changes: 16 additions & 0 deletions clang/test/CodeGenOpenCL/amdgpu-readonly-features-written-with-no-target.cl
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@@ -0,0 +1,16 @@
// REQUIRES: amdgpu-registered-target

// Check the readonly feature will can be written to the IR
// if there is no target specified.

// RUN: %clang_cc1 -triple amdgcn -emit-llvm -o - %s | FileCheck --check-prefix=NOCPU %s
// RUN: %clang_cc1 -triple amdgcn -target-cpu gfx942 -emit-llvm -o - %s | FileCheck --check-prefix=GFX942 %s
// RUN: %clang_cc1 -triple amdgcn -target-cpu gfx1100 -emit-llvm -o - %s | FileCheck --check-prefix=GFX1100 %s
// RUN: %clang_cc1 -triple amdgcn -target-cpu gfx1200 -emit-llvm -o - %s | FileCheck --check-prefix=GFX1200 %s

__attribute__((target("gws,image-insts,vmem-to-lds-load-insts"))) void test() {}

// NOCPU: "target-features"="+gws,+image-insts,+vmem-to-lds-load-insts"
// GFX942: "target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+fp8-conversion-insts,+fp8-insts,+gfx8-insts,+gfx9-insts,+gfx90a-insts,+gfx940-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64,+xf32-insts"
// GFX1100: "target-features"="+16-bit-insts,+atomic-fadd-rtn-insts,+ci-insts,+dl-insts,+dot10-insts,+dot12-insts,+dot5-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize32"
// GFX1200: "target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-buffer-pk-add-bf16-inst,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot10-insts,+dot11-insts,+dot12-insts,+dot7-insts,+dot8-insts,+dot9-insts,+dpp,+fp8-conversion-insts,+gfx10-3-insts,+gfx10-insts,+gfx11-insts,+gfx12-insts,+gfx8-insts,+gfx9-insts,+wavefrontsize32"