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The original use case was simulating bits of Verilog vendor IP in an otherwise VHDL design (e.g. #1227 or #1207). I'm slowly making the backend more Verilog-aware (e.g. it now has active/inactive/NBA scheduling regions so Verilog testbenches that rely on this should work properly) and I'm not opposed to adding more SV features but realistically it's going to be a while before it supports everything required for UVM.
There's a very minimal VPI implementation but at the moment it's just there to implement system tasks like |
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Hi, I noticed you recently started working on Verilog support and wondered what the end goal of this project is. Just sufficient (System)Verilog support to cover most synthesizable code, like what Icarus hopes to be. Or will it try to cover all of SV to support things like UVM?
What's the status of the VPI? Is it stable enough to start testing?
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