Search results

Low performance when simulating large netlists

Status: Open.

#1341 In nickg/nvc;

· jorkrohn opened on Nov 6, 2025

Wrong signal in FST file

Status: Open.

#1340 In nickg/nvc;

· lemmuh opened on Nov 5, 2025

Incorrect squaring of integers for a*a vs. a**2

Status: Open.

#1338 In nickg/nvc;

· m-tosch opened on Nov 4, 2025

Is it possible to use accent for displaying text with string ?

Status: Open.

#1337 In nickg/nvc;

· Martoni opened on Nov 1, 2025

[Verilog] fatal: cannot calculate longest static prefix

Status: Open.

#1336 In nickg/nvc;

· mik1234mc opened on Oct 29, 2025

Get "expecting type mark while parsing qualified expression" when using subtype of element

Status: Open.

#1335 In nickg/nvc;

· avelure opened on Oct 28, 2025

Verilog - Unconnected port causes error

verilog

Status: Open.

#1333 In nickg/nvc;

· Blebowski opened on Oct 24, 2025

Is it possible to simulate large VHDL netlists in nvc?

Status: Open.

#1331 In nickg/nvc;

· mik1234mc opened on Oct 24, 2025

crash maybe around generic procedures with view interfaces

2019

crash

Status: Open.

#1328 In nickg/nvc;

· nathanaelhuffman opened on Oct 21, 2025

Verilog generate statement support

verilog

Status: Open.

#1326 In nickg/nvc;

· mik1234mc opened on Oct 17, 2025

Compiling Xilinx libraries in Windows command prompt failed:

Status: Open.

#1324 In nickg/nvc;

· ugrossm opened on Oct 16, 2025

Black-box

wishlist

Status: Open.

#1322 In nickg/nvc;

· Blebowski opened on Oct 13, 2025