Black-box

[Blebowski]

Hi,

It would be useful to have support for "black-box" instances. There would exists a "special list" of entities / modules
(passed e.g. via CLI switch or some other config). If NVC elaborates a design, and encounters instance for which it
can't locate the design unit (by whatever binding mechanism), it would not Error out, but it would simply throw warning,
but managed to elaborate the design.

Such "black-box" instance could behave in several different ways:

• If there is a component existing for the instance (component binding indication), but not the entity, port directions are known.
• If component does not exist for the instance (entity binding indication), port directions are not known.

If port directions are known, inputs have no effect for rest of the design (as-if they were floating in the black-box),
outputs of the black-box would be "as-if" driven to sth. like TYPE'left -> For std_logic types this would be having driver with default
U value.

For verilog, the default value of outputs could be X.

The use-case for this is, when you have large design that is just being developed, and you e.g. don't have analog models available,
or some of the RTL still does not exist, you could run the simulation without the need to create "dummy envelopes". This is handy
since sometimes such "dummy envelopes" may be forgotten, and stay there (especially when there is lack of time for verification).

I know a commercial debugger that has such feature that it can elaborate incomplete design and show schematics. Very handy
when the design is incomplete, you are waiting for some of its parts, but want to work on the rest.

[NikLeberg]

Just my 2 cents: I have been bitten by ModelSim defaulting to treat not defined entities like such black boxes and I didn't notice the warning right away. So I'd highly suggest to really only enable this with a specific CLI flag like --enable-blackboxing or with a list of allowed entities.

[nickg]

Isn't this exactly the behaviour you get now with unbound components? It should produce a warning during elaboration and in simulation all outputs have default values.

[Blebowski]

I must admit I did not check that.

Btw. do you know if throwing a warning is according to LRM ? If so can you please post the section describing this, I did not find this behavior specified.

IMHO, the good would be following:

• Default on unbound instance is to throw error
• There would exist some switch (e.g. --allow-black-boxes). If this switch is passed without any argument, then any unbound instances behave as before (and the warning is still exists, could eventually be supressed if this is ever implemented: Feature request: Warning suppression and escalation to error command-line flags #1004).
• If the switch contains a list of modules/entities that shall be treated as black-boxes, then only those instaces are treated as black-boxes (and the warning is still printed for these instances). e.g. --black-boxes=module_a,entity_a.

The behavior would be the same for VHDL as well as Verilog modules. If there was an entity binding indication used to specify the entity for instance, this would not be possible since the entity / module already needs to be analyzed before.

IMHO this would be the most generic approach that would avoid overlooking the black-boxes if undesired, while still providing fine-grained capability to specify the "desired black-boxes".