Introduce job queues for source/sink modules

Bender.yml

@@ -33,7 +33,7 @@ sources:
       - rtl/core/hci_core_mux_ooo.sv
       - rtl/core/hci_core_r_valid_filter.sv
       - rtl/core/hci_core_r_id_filter.sv
-      - rtl/core/hci_core_source.sv
+      - rtl/core/hci_core_source_v2.sv
       - rtl/core/hci_core_split.sv
       - rtl/interco/hci_log_interconnect.sv
       - rtl/interco/hci_log_interconnect_l2.sv
@@ -42,6 +42,7 @@ sources:
       - rtl/interco/hci_router_reorder.sv
       # Level 3
       - rtl/core/hci_core_sink.sv
+      - rtl/core/hci_core_sink_v2.sv
       - rtl/interco/hci_router.sv
       # Level 4
       - rtl/hci_interconnect.sv

rtl/common/hci_package.sv

@@ -49,7 +49,8 @@ package hci_package;
     logic [7:0] low_prio_max_stall;
   } hci_interconnect_ctrl_t;
 
-  typedef struct packed {
+
+typedef struct packed {
     logic                                     req_start;
     hwpe_stream_package::ctrl_addressgen_v3_t addressgen_ctrl;
   } hci_streamer_ctrl_t;
@@ -60,8 +61,19 @@ package hci_package;
     hwpe_stream_package::flags_addressgen_v3_t addressgen_flags;
   } hci_streamer_flags_t;
 
+  typedef struct packed {
+    logic                                     valid;
+    hwpe_stream_package::ctrl_addressgen_v3_t addressgen_ctrl;
+  } hci_streamer_v2_ctrl_t;
+
+  typedef struct packed {
+    logic                                      ready;
+    logic                                      done;
+    hwpe_stream_package::flags_addressgen_v3_t addressgen_flags;
+  } hci_streamer_v2_flags_t;
+
   typedef enum {
-    STREAMER_IDLE, STREAMER_WORKING, STREAMER_DONE
+    STREAMER_IDLE, STREAMER_PRESAMPLE ,STREAMER_WORKING, STREAMER_DONE
   } hci_streamer_state_t;
 
 endpackage // hci_package

rtl/core/hci_core_sink.sv

@@ -354,4 +354,4 @@ module hci_core_sink
 `endif
 `endif
 
-endmodule // hci_core_sink
+endmodule // hci_core_sink