Skip to content

Fix FIFO delay parameter propagation in HCI #63

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: master
Choose a base branch
from
Open

Fix FIFO delay parameter propagation in HCI #63

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
8 changes: 6 additions & 2 deletions rtl/common/hci_helpers.svh
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -206,6 +206,7 @@
`define HCI_SIZE_GET_IW(__x) (`HCI_SIZE_PARAM(__x).IW)
`define HCI_SIZE_GET_EW(__x) (`HCI_SIZE_PARAM(__x).EW)
`define HCI_SIZE_GET_EHW(__x) (`HCI_SIZE_PARAM(__x).EHW)
`define HCI_SIZE_GET_FD(__x) (`HCI_SIZE_PARAM(__x).FD)

// Shorthand for defining a HCI interface compatible with a parameter
`define HCI_INTF_EXPLICIT_PARAM(__name, __clk, __param) \
Expand All @@ -216,7 +217,8 @@
.UW ( __param.UW ), \
.IW ( __param.IW ), \
.EW ( __param.EW ), \
.EHW ( __param.EHW ) \
.EHW ( __param.EHW ), \
.FD ( __param.FD ) \
) __name ( \
.clk ( __clk ) \
)
Expand All @@ -231,6 +233,7 @@
`define HCI_SIZE_GET_IW_CHECK(__x) (__x.IW)
`define HCI_SIZE_GET_EW_CHECK(__x) (__x.EW)
`define HCI_SIZE_GET_EHW_CHECK(__x) (__x.EHW)
`define HCI_SIZE_GET_FD_CHECK(__x) (__x.FD)

// Asserts (generic definition usable with any parameter name)
`define HCI_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(__xparam, __xintf) \
Expand All @@ -240,7 +243,8 @@
initial __xparam``_intf_size_check_uw : assert(__xparam.UW == `HCI_SIZE_GET_UW_CHECK(__xintf)); \
initial __xparam``_intf_size_check_iw : assert(__xparam.IW == `HCI_SIZE_GET_IW_CHECK(__xintf)); \
initial __xparam``_intf_size_check_ew : assert(__xparam.EW == `HCI_SIZE_GET_EW_CHECK(__xintf)); \
initial __xparam``_intf_size_check_ehw : assert(__xparam.EHW == `HCI_SIZE_GET_EHW_CHECK(__xintf))
initial __xparam``_intf_size_check_ehw : assert(__xparam.EHW == `HCI_SIZE_GET_EHW_CHECK(__xintf)); \
initial __xparam``_intf_size_check_fd : assert(__xparam.FD == `HCI_SIZE_GET_FD_CHECK(__xintf))

// Asserts (specialized definition for conventional param names
`define HCI_SIZE_CHECK_ASSERTS(__intf) `HCI_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(`HCI_SIZE_PARAM(__intf), __intf)
Expand Down
1 change: 1 addition & 0 deletions rtl/common/hci_interfaces.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,7 @@ interface hci_core_intf (
parameter int unsigned IW = hci_package::DEFAULT_IW; /// ID Width
parameter int unsigned EW = hci_package::DEFAULT_EW; /// ECC Width
parameter int unsigned EHW = hci_package::DEFAULT_EHW; /// Handshake ECC Width
parameter int unsigned FD = hci_package::DEFAULT_FD; /// FIFO Depth

// handshake signals
logic req;
Expand Down
5 changes: 4 additions & 1 deletion rtl/common/hci_package.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@ package hci_package;
parameter int unsigned DEFAULT_IW = 8; // Default ID Width
parameter int unsigned DEFAULT_EW = 1; // Default ECC for Data Width
parameter int unsigned DEFAULT_EHW = 1; // Default ECC for Handhshake Width
parameter int unsigned DEFAULT_FD = 0; // Default FIFO Depth

typedef struct packed {
int unsigned DW;
Expand All @@ -36,6 +37,7 @@ package hci_package;
int unsigned IW;
int unsigned EW;
int unsigned EHW;
int unsigned FD;
} hci_size_parameter_t;

parameter hci_size_parameter_t DEFAULT_HCI_SIZE = '{
Expand All @@ -45,7 +47,8 @@ package hci_package;
UW : DEFAULT_UW,
IW : DEFAULT_IW,
EW : DEFAULT_EW,
EHW : DEFAULT_EHW
EHW : DEFAULT_EHW,
FD : DEFAULT_FD
};

typedef struct packed {
Expand Down
9 changes: 8 additions & 1 deletion rtl/core/hci_core_mux_static.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -153,7 +153,14 @@ module hci_core_mux_static
ehw : assert(in[i].EHW == out.EHW);
end

`HCI_SIZE_CHECK_ASSERTS_EXPLICIT_PARAM(`HCI_SIZE_PARAM(in), in[0]);
initial HCI_SIZE_in_intf_size_check_dw : assert(`HCI_SIZE_PARAM(in).DW == in[0].DW);
initial HCI_SIZE_in_intf_size_check_bw : assert(`HCI_SIZE_PARAM(in).BW == in[0].BW);
initial HCI_SIZE_in_intf_size_check_aw : assert(`HCI_SIZE_PARAM(in).AW == in[0].AW);
initial HCI_SIZE_in_intf_size_check_uw : assert(`HCI_SIZE_PARAM(in).UW == in[0].UW);
initial HCI_SIZE_in_intf_size_check_iw : assert(`HCI_SIZE_PARAM(in).IW == in[0].IW);
initial HCI_SIZE_in_intf_size_check_ew : assert(`HCI_SIZE_PARAM(in).EW == in[0].EW);
initial HCI_SIZE_in_intf_size_check_ehw : assert(`HCI_SIZE_PARAM(in).EHW == in[0].EHW);
// initial HCI_SIZE_in_intf_size_check_fd : assert(`HCI_SIZE_PARAM(in).FD == in[0].FD);

`endif
`endif
Expand Down
11 changes: 7 additions & 4 deletions rtl/core/hci_core_r_id_filter.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -26,9 +26,7 @@ module hci_core_r_id_filter
import hwpe_stream_package::*;
import hci_package::*;
#(
parameter hci_size_parameter_t `HCI_SIZE_PARAM(tcdm_target) = '0,
parameter int unsigned N_OUTSTANDING = 2,
parameter bit MULTICYCLE_SUPPORT = 1'b0
parameter hci_size_parameter_t `HCI_SIZE_PARAM(tcdm_target) = '0
)
(
input logic clk_i,
Expand All @@ -41,6 +39,8 @@ module hci_core_r_id_filter

localparam int unsigned IW = `HCI_SIZE_GET_IW(tcdm_target);
localparam int unsigned EHW = `HCI_SIZE_GET_EHW(tcdm_target);
localparam int unsigned FD = `HCI_SIZE_GET_FD(tcdm_target);
localparam bit MULTICYCLE_SUPPORT = (FD > 1);

logic [IW-1:0] target_r_id;

Expand Down Expand Up @@ -69,7 +69,7 @@ module hci_core_r_id_filter
fifo_v3 #(
.FALL_THROUGH(1'b0),
.DATA_WIDTH(IW),
.DEPTH(N_OUTSTANDING)
.DEPTH(FD)
) i_r_id_fifo (
.clk_i,
.rst_ni,
Expand Down Expand Up @@ -129,6 +129,8 @@ module hci_core_r_id_filter
`ifndef SYNTHESIS
`ifndef VERILATOR
`ifndef VCS
// Only check single-cycle timing when FD = 1 (no multicycle support)
if (!MULTICYCLE_SUPPORT) begin : single_cycle_asserts
// gnt=1 & wen=1 => the following cycle r_valid=1
property p_gnt_wen_high_then_r_valid_high_next_cycle;
@(posedge clk_i) (tcdm_initiator.gnt && tcdm_initiator.wen) |-> ##1 tcdm_initiator.r_valid;
Expand All @@ -144,6 +146,7 @@ module hci_core_r_id_filter

assert_gnt_low_then_r_valid_low_next_cycle: assert property (p_gnt_low_then_r_valid_low_next_cycle)
else $warning("`r_valid` did not follow `gnt` by 1 cycle in a read: are you sure the `r_id` filter is at the 1-cycle latency boundary?");
end : single_cycle_asserts
`endif
`endif
`endif
Expand Down
8 changes: 3 additions & 5 deletions rtl/ecc/hci_ecc_interconnect.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,12 +42,10 @@
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
* | *IW* | `N_HWPE+N_CORE+N_DMA+N_EXT` | ID Width. |
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
* | *EXPFIFO* | 0 | Depth of HCI router FIFO. |
* | *FD* | 0 | Depth of HCI router FIFO. |
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
* | *SEL_LIC* | 0 | Kind of LIC to instantiate (0=regular L1, 1=L2). |
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
* | *CHUNK_SIZE* | 32 | Width in bits of each chunk of data to protect individually. |
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
*/

`include "hci_helpers.svh"
Expand All @@ -63,7 +61,6 @@ module hci_ecc_interconnect
parameter int unsigned N_MEM = 16 , // Number of Memory banks
parameter int unsigned TS_BIT = 21 , // TEST_SET_BIT (for Log Interconnect)
parameter int unsigned IW = N_HWPE+N_CORE+N_DMA+N_EXT, // ID Width
parameter int unsigned EXPFIFO = 0 , // FIFO Depth for HWPE Interconnect
parameter int unsigned SEL_LIC = 0 , // Log interconnect type selector
parameter int unsigned FILTER_WRITE_R_VALID[0:N_HWPE-1] = '{default: 0},
parameter int unsigned CHUNK_SIZE = 32 , // Chunk size of data to be encoded separately (HWPE branch)
Expand Down Expand Up @@ -98,6 +95,7 @@ module hci_ecc_interconnect
localparam int unsigned BWH = `HCI_SIZE_GET_BW(hwpe);
localparam int unsigned UWH = `HCI_SIZE_GET_UW(hwpe);
localparam int unsigned EWH = `HCI_SIZE_GET_EW(hwpe);
localparam int unsigned FDH = `HCI_SIZE_GET_FD(hwpe);
localparam int unsigned N_CHUNK = DWH / CHUNK_SIZE;
localparam int unsigned EW_DW = $clog2(CHUNK_SIZE)+2;

Expand Down Expand Up @@ -362,7 +360,7 @@ module hci_ecc_interconnect
);

hci_router #(
.FIFO_DEPTH ( EXPFIFO ),
.FIFO_DEPTH ( FDH ),
.NB_OUT_CHAN ( N_MEM ),
.USE_ECC ( 1 ),
.FILTER_WRITE_R_VALID ( FILTER_WRITE_R_VALID[0] ),
Expand Down
21 changes: 13 additions & 8 deletions rtl/hci_interconnect.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
* | *IW* | `N_HWPE+N_CORE+N_DMA+N_EXT` | ID Width. |
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
* | *EXPFIFO* | 0 | Depth of HCI router FIFO. |
* | *FD* | 0 | Depth of HCI router FIFO. |
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
* | *SEL_LIC* | 0 | Kind of LIC to instantiate (0=regular L1, 1=L2). |
* +---------------------+-----------------------------+----------------------------------------------------------------------------------+
Expand All @@ -60,7 +60,6 @@ module hci_interconnect
parameter int unsigned N_MEM = 16 , // Number of Memory banks
parameter int unsigned TS_BIT = 21 , // TEST_SET_BIT (for Log Interconnect)
parameter int unsigned IW = N_HWPE+N_CORE+N_DMA+N_EXT, // ID Width
parameter int unsigned EXPFIFO = 0 , // FIFO Depth for HWPE Interconnect
parameter int unsigned SEL_LIC = 0 , // Log interconnect type selector
parameter int unsigned FILTER_WRITE_R_VALID[0:N_HWPE-1] = '{default: 0},
parameter hci_size_parameter_t `HCI_SIZE_PARAM(cores) = '0,
Expand Down Expand Up @@ -93,6 +92,7 @@ module hci_interconnect
localparam int unsigned BWH = `HCI_SIZE_GET_BW(hwpe);
localparam int unsigned UWH = `HCI_SIZE_GET_UW(hwpe);
localparam int unsigned IWH = `HCI_SIZE_GET_IW(hwpe);
localparam int unsigned FDH = `HCI_SIZE_GET_FD(hwpe);

localparam hci_size_parameter_t `HCI_SIZE_PARAM(all_except_hwpe) = '{
DW: DEFAULT_DW,
Expand All @@ -101,7 +101,8 @@ module hci_interconnect
UW: UW_LIC,
IW: DEFAULT_IW,
EW: DEFAULT_EW,
EHW: DEFAULT_EHW
EHW: DEFAULT_EHW,
FD: DEFAULT_FD
};
hci_core_intf #(
.DW ( DEFAULT_DW ),
Expand Down Expand Up @@ -129,7 +130,8 @@ module hci_interconnect
UW: UW_LIC,
IW: IW,
EW: DEFAULT_EW,
EHW: DEFAULT_EHW
EHW: DEFAULT_EHW,
FD: DEFAULT_FD
};
`HCI_INTF_ARRAY(all_except_hwpe_mem, clk_i, 0:N_MEM-1);

Expand All @@ -140,7 +142,8 @@ module hci_interconnect
UW: UW_LIC,
IW: IW,
EW: DEFAULT_EW,
EHW: DEFAULT_EHW
EHW: DEFAULT_EHW,
FD: DEFAULT_FD
};
`HCI_INTF_ARRAY(hwpe_mem_muxed, clk_i, 0:N_MEM-1);

Expand All @@ -152,7 +155,8 @@ module hci_interconnect
UW: UW_LIC,
IW: IW,
EW: DEFAULT_EW,
EHW: DEFAULT_EHW
EHW: DEFAULT_EHW,
FD: DEFAULT_FD
};
`HCI_INTF_ARRAY(hwpe_mem, clk_i, 0:N_HWPE*N_MEM-1);

Expand All @@ -165,7 +169,8 @@ module hci_interconnect
.UW(UWH),
.IW(IWH),
.EW(DEFAULT_EW),
.EHW(DEFAULT_EHW)
.EHW(DEFAULT_EHW),
.FD(FDH)
) hwpe_to_router (
.clk(clk_i)
);
Expand Down Expand Up @@ -239,7 +244,7 @@ module hci_interconnect
for(genvar ii=0; ii<N_HWPE; ii++) begin : hwpe_req2mem

hci_router #(
.FIFO_DEPTH ( EXPFIFO ),
.FIFO_DEPTH ( FDH ),
.NB_OUT_CHAN ( N_MEM ),
.FILTER_WRITE_R_VALID ( FILTER_WRITE_R_VALID[ii] ),
.`HCI_SIZE_PARAM(in) ( `HCI_SIZE_PARAM(hwpe) ),
Expand Down