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@sermazz sermazz commented Aug 29, 2025

This merges #89 and #99

  • up-to-date dmac_wrap for iDMA
  • Parametrizable wide AXI port to route iDMA requests to outer world (instead of going through the narrow cluster bus and narrow AXI ports)
  • Multiple HWPE support for HCI
  • iDMA transfers to/from TCDM can now go through wide HWPEs port of TCDM

Important notes

  • HCI and Neureka dependencies now point to the upstream main versions (with our updates), rather than to the Astral-specific versions with hardcoded ECC features. This would require manual merge if desired
  • ECC and HMR features and testing are disabled due to the point above (both in hw and sw)
  • Many features are difficult to test in multiple configurations in the CI, e.g., even if the type/number of HWPE is easily parametrizable, those parameters do not propagate to runtime and regression tests, which need different revisions to correctly test different hardware configurations. In this PR we only test one configuration (e.g., only Neureka, no other HWPEs, no ECC features and fault testing, ...), overwriting the one from Astral. We should figure out a way to facilitate this.

To do

@DanielKellerM

sermazz and others added 30 commits August 28, 2025 16:23
The linker script has L1 address ORIGIN set to 0x10000004 even through
in hardware it is set to 0x10000000. However the testbench assumes 64b
alignment to initialize the L1. Thus, the data was shifted by 32b in the
simulation. While the AXI bursts are set to 64b, the misalignment needs
to be handled coming from the linker script.
Being unnecessarily unpacked, it was not compatible with other systems (like Cheshire)
It created problems in routing of requests through peripheral interconnect
… configurations based on WidePortShouldBeEnabled. Update AXI request/response handling and introduce a multiplexer for merging cluster bus and DMA narrow master requests. Enhance isolation and CDC instantiation for wide port scenarios.
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
DanielKellerM and others added 12 commits August 29, 2025 10:47
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…ncy in DMA configuration

Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…PE_PORT also in the package as reference

Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
… for Questa

Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…ke hex; roll back to astral version Neureka; 3 HWPEs added

Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…lized

Signed-off-by: Daniel Keller <daniel.kellermartinez@csem.ch>
…arameters

- Update HCI interface parameter structure to correctly propagate the
FIFO depth parameter to both the interconnect and the HWPE (Neureka)
- Increase the FIFO depth parameter from 0 to 2 to fix the combinational
loop due to iDMA being able to read+write from+to TCDM with its 2
backend
- Bump versions of HCI and Neureka in bender for updated parameter
structure
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3 participants