Digital Logic Modules in Verilog

Digital Design and Computer Organisation

This repository showcases foundational modules in Verilog, each with modularity, and simulation-ready structure. From encoders and decoders to demultiplexers, every component is tested, documented, and ready to plug into larger systems.

Folder Overview

Folder	Description
Adders/	Half and full adders with simulation and waveform files
Decoder/	2-to-4 binary decoder with testbench and GTKWave output
Demultiplexer/	1-to-2 and 1-to-4 demux modules with simulations
Encoder/	4-to-2 binary encoder with testbench and waveform
Logic Gates/	Basic gates (AND, OR, NOT, etc.) implemented in Verilog
Multiplexer/	MUX modules with varying input sizes and verification

Each folder includes:

• Verilog source files (.v)
• Testbenches (_tb.v)
• Simulation outputs (_sim)
• Waveform files (.vcd) viewable in GTKWave

Tools Used

• Icarus Verilog for simulation and module design
• GTKWave for waveform visualization

Compile and Run the code

Compile the main file and testbench:

iverilog -o <output name> <main file.v> <testbench file.v>

Run the simulation:

vvp <output name>

After running the above code you will able to see vvp output

View waveform in GTKWave:

gtkwave <output vcd file>