A study in MIPS microarchitecture trade-offs. This project implements three CPU designs: a single-cycle, a hardware-scheduled multicycle, and a software-scheduled pipelined core; then documents and contrasts their performance/complexity. Source is organized by variant (src_sc, src_hw, src_sw) with dedicated testbenches and write-ups.

This is a simple CPU emulator with custom architecture

This is a simulation of the MIPS32 Single Cycle Processor on Xilinx ISE written in Verilog.

RISC-V Pipelined Processor simulation in Verilog on Xilinx ISE

custom CPU emulator and assembler

RISCV 40 Instruction Cycle Accurate CPU Model

Computer Organization I exercises

design of an 8-bit MPU