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drivers: ethernet: stm32n6: Fix compilation after refactoring #96845

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Merged
merged 4 commits into from
Oct 3, 2025
Merged

drivers: ethernet: stm32n6: Fix compilation after refactoring #96845

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9b80bd1
drivers: ethernet: stm32n6: Fix phy modes declarations
erwango Oct 1, 2025
6328b1f
drivers: ethernet: stm32n6: Remove attributes from extern definitions
erwango Oct 1, 2025
2ea266d
drivers: ethernet: stm32n6: Use zephyr symbol for alignment attribute
erwango Oct 1, 2025
f90a595
boards: st: stm32n6 boards: Add netif:eth twister support
erwango Oct 1, 2025
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1 change: 1 addition & 0 deletions boards/st/nucleo_n657x0_q/twister.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ supported:
- dma
- i2c
- gpio
- netif:eth
- spi
- uart
- usb_device
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3 changes: 2 additions & 1 deletion boards/st/stm32n6570_dk/twister.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,9 @@ supported:
- dma
- i2c
- gpio
- pwm
- memc
- netif:eth
- pwm
- spi
- uart
- usb_device
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4 changes: 2 additions & 2 deletions drivers/ethernet/eth_stm32_hal_common.c
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Original file line number Diff line number Diff line change
Expand Up @@ -46,8 +46,8 @@ uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_STM32_RX_BUF_SIZE] __eth_stm32_buf;
uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_STM32_TX_BUF_SIZE] __eth_stm32_buf;

#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
ETH_DMADescTypeDef dma_rx_desc_tab[ETH_DMA_RX_CH_CNT][ETH_RXBUFNB] ALIGN_32BYTES(__eth_stm32_desc);
ETH_DMADescTypeDef dma_tx_desc_tab[ETH_DMA_TX_CH_CNT][ETH_TXBUFNB] ALIGN_32BYTES(__eth_stm32_desc);
ETH_DMADescTypeDef dma_rx_desc_tab[ETH_DMA_RX_CH_CNT][ETH_RXBUFNB] __eth_stm32_desc __aligned(32);
ETH_DMADescTypeDef dma_tx_desc_tab[ETH_DMA_TX_CH_CNT][ETH_TXBUFNB] __eth_stm32_desc __aligned(32);
#else
ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] __eth_stm32_desc;
ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] __eth_stm32_desc;
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42 changes: 22 additions & 20 deletions drivers/ethernet/eth_stm32_hal_priv.h
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Expand Up @@ -44,18 +44,6 @@ extern const struct device *eth_stm32_phy_dev;
#define __eth_stm32_buf __aligned(4)
#endif

#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
#define STM32_ETH_PHY_MODE(inst) \
((DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, rgmii) ? ETH_RGMII_MODE : \
(DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, gmii) ? ETH_GMII_MODE : \
(DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, mii) ? ETH_MII_MODE : \
ETH_RMII_MODE))))
#else
#define STM32_ETH_PHY_MODE(inst) \
(DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, mii) ? \
ETH_MII_MODE : ETH_RMII_MODE)
#endif

#if defined(CONFIG_ETH_STM32_HAL_API_V1)

#define ETH_MII_MODE ETH_MEDIA_INTERFACE_MII
Expand All @@ -77,23 +65,37 @@ struct eth_stm32_tx_context {

#endif /* CONFIG_ETH_STM32_HAL_API_V2 */

#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)

#define ETH_GMII_MODE HAL_ETH_GMII_MODE
#define ETH_RGMII_MODE HAL_ETH_RGMII_MODE

#define STM32_ETH_PHY_MODE(inst) \
((DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, rgmii) ? ETH_RGMII_MODE : \
(DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, gmii) ? ETH_GMII_MODE : \
(DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, mii) ? ETH_MII_MODE : \
ETH_RMII_MODE))))
#else
#define STM32_ETH_PHY_MODE(inst) \
(DT_INST_ENUM_HAS_VALUE(inst, phy_connection_type, mii) ? \
ETH_MII_MODE : ETH_RMII_MODE)
#endif

/* Definition of the Ethernet driver buffers size and count */
#define ETH_STM32_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
#define ETH_STM32_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */

BUILD_ASSERT(ETH_STM32_RX_BUF_SIZE % 4 == 0, "Rx buffer size must be a multiple of 4");

extern uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_STM32_RX_BUF_SIZE] __eth_stm32_buf;
extern uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_STM32_TX_BUF_SIZE] __eth_stm32_buf;
extern uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_STM32_RX_BUF_SIZE];
extern uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_STM32_TX_BUF_SIZE];

#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
extern ETH_DMADescTypeDef dma_rx_desc_tab[ETH_DMA_RX_CH_CNT][ETH_RXBUFNB]
ALIGN_32BYTES(__eth_stm32_desc);
extern ETH_DMADescTypeDef dma_tx_desc_tab[ETH_DMA_TX_CH_CNT][ETH_TXBUFNB]
ALIGN_32BYTES(__eth_stm32_desc);
extern ETH_DMADescTypeDef dma_rx_desc_tab[ETH_DMA_RX_CH_CNT][ETH_RXBUFNB];
extern ETH_DMADescTypeDef dma_tx_desc_tab[ETH_DMA_TX_CH_CNT][ETH_TXBUFNB];
#else
extern ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] __eth_stm32_desc;
extern ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] __eth_stm32_desc;
extern ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB];
extern ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB];
#endif

/* Device constant configuration parameters */
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5 changes: 0 additions & 5 deletions drivers/ethernet/eth_stm32_hal_v2.c
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Original file line number Diff line number Diff line change
Expand Up @@ -19,11 +19,6 @@

LOG_MODULE_DECLARE(eth_stm32_hal, CONFIG_ETHERNET_LOG_LEVEL);

#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
#define ETH_GMII_MODE HAL_ETH_GMII_MODE
#define ETH_RGMII_MODE HAL_ETH_RGMII_MODE
#endif

#define ETH_DMA_TX_TIMEOUT_MS 20U /* transmit timeout in milliseconds */

struct eth_stm32_rx_buffer_header {
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