ARM64 FVP Board Unification and ARMv9-A Support #96852

npitre · 2025-10-01T11:35:41Z

This series modernizes ARM64 Fixed Virtual Platform (FVP) board support with
ARMv9-A enablement and unified board structure.

Changes:

Unified Board Structure - Cleaner hierarchical naming replacing verbose board
names (fvp_base_revc_2xaem/{v8a,v9a,a320} with SMP variants)
ARMv9-A base architecture support with Cortex-A510 CPU by default
Specific Cortex A320 (ARMv9.2-A) CPU support
ARM FVP CPU power management driver to enable SMP on bare metal
Comprehensive ARM architecture feature detection test

Late additions for the full CI to pass:

Scalable Vector Extension (SVE) context switching
SVE context switching validation test
Fix for the nested IRQ test using NS execution and TF-A

nordicjm · 2025-10-02T07:58:55Z

soc/arm/fvp_aem/Kconfig


-config SOC_FVP_BASE_REVC_2XAEMV8A
+config SOC_FVP_V8A
+	bool


Suggested change

bool

nordicjm · 2025-10-02T08:00:18Z

boards/arm/fvp_base_revc_2xaem/doc/index.rst

+Board Variants
+==============
+
+This board configuration supports multiple architecture variants:


Suggested change

This board configuration supports multiple architecture variants:

The following board targets are available:

or other reword to remove configuration

nordicjm · 2025-10-02T08:00:56Z

boards/arm/fvp_base_revc_2xaem/doc/index.rst

+The legacy board name ``fvp_base_revc_2xaemv8a`` has been replaced with the
+unified ``fvp_base_revc_2xaem/v8a`` naming. Update your build commands:
+
+* Old: ``west build -b fvp_base_revc_2xaemv8a``
+* New: ``west build -b fvp_base_revc_2xaem/v8a``
+
+The legacy board name remains supported for backward compatibility.


this is a no, use the deprecated board feature

nordicjm · 2025-10-02T08:02:56Z

boards/arm/fvp_base_revc_2xaem/Kconfig.fvp_base_revc_2xaem

 # SPDX-License-Identifier: Apache-2.0

 config BOARD_FVP_BASE_REVC_2XAEM
+	bool


Suggested change

bool

NEVER declare these auto generated symbols, same goes for all below

nordicjm · 2025-10-02T08:04:14Z

boards/arm/fvp_base_revc_2xaem/Kconfig.fvp_base_revc_2xaem

+	bool
+	default y if BOARD_QUALIFIERS = "a320"


nordicjm · 2025-10-02T08:04:45Z

boards/arm/fvp_base_revc_2xaem/doc/index.rst

+
+**Cortex-A320 Configuration:**
+
+The ``a320`` variant provides Cortex-A320 specific FVP configuration with:


use full name and call board target

nordicjm · 2025-10-02T08:05:13Z

cmake/gcc-m-cpu.cmake

+    # Use cortex-a710 as fallback since both are high-performance ARMv9-A cores with similar features
+    # TODO: Update to use cortex-a320 when GCC support is added (likely in GCC 15 or 16)
+    set(GCC_M_CPU cortex-a710)
+    message(STATUS "Using cortex-a710 as fallback for cortex-a320 (not yet supported in GCC)")


@stephanosio

nordicjm · 2025-10-02T08:05:59Z

drivers/pm_cpu_ops/Kconfig


+config PM_CPU_OPS_FVP
+	bool "Support for ARM FVP CPU power management"
+	depends on BOARD_FVP_BASE_REVC_2XAEMV8A && !PM_CPU_OPS_PSCI


drivers should not depend on boards, use proper DT_* or select it from a Kconfig file in the board

nordicjm · 2025-10-02T08:06:23Z

drivers/pm_cpu_ops/pm_cpu_ops_fvp.c

+	/* Read the status for the selected CPU */
+	return sys_read32(pwrc_vaddr + PWRC_PSYSR_OFF);
+}
+


Suggested change

wearyzen · 2025-10-02T10:15:04Z

Just a query not a change request: what do you think about moving boards to a separate boards/arm/fvp directory so that fvp_base_revc_2xaem/v8a becomes fvp/base_revc_2xaem/v8a? Later this fvp directory could be used to add other fvp boards similar to what qemu has.

nashif · 2025-10-03T13:15:14Z

Hi, it would be nice to have a maintainer for the ARM64 arch, this is now vacant :(

zephyr/MAINTAINERS.yml

Line 239 in 36bc2f3

ARM64 arch:

npitre · 2025-10-03T13:42:59Z

Hi, it would be nice to have a maintainer for the ARM64 arch, this is now vacant :(

I could step in ... however I have yet more patches to submit and without other people to review them this remains a problem.

Change SGI interrupt lines from 14-15 to 6-7 for nested interrupt testing. SGI 8-15 are unaccessible from Non-Secure state (e.g., when running with TF-A), causing test failures. SGI 0-2 are reserved for Zephyr SMP IPIs, so use SGI 6-7 which work in both Secure and Non-Secure configurations. Fixes test failure: "isr0 did not execute" assertion at line 184. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add a new PM CPU ops driver for ARM Fixed Virtual Platform (FVP) that enables bare metal SMP support without ARM Trusted Firmware (ATF). The driver provides CPU power-on and system reset operations by directly interfacing with FVP's power controller (PWRC) and V2M system registers. The implementation includes RVBAR_EL3 configuration to redirect secondary CPU reset vectors to Zephyr's image header, enabling proper SMP initialization without firmware assistance. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

This adds necessary configuration files to build with SMP and no trusted firmware. Given PSCI is not available, CPU power management uses the FVP power controller directly. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Reorganize fvp_aemv8a SOC into unified fvp_aem series with a v8a architecture variants to enable cleaner board target naming. This also sets the stage for upcoming ARMv9-A support. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Create unified board configuration to replace verbose board naming with shorter hierarchical structure. This board works with the new unified fvp_aem SOC series and supports the v8a architecture variant. This enables board targets like: - fvp_base_revc_2xaem/v8a (basic ARMv8-A) - fvp_base_revc_2xaem/v8a/smp (ARMv8-A SMP) - fvp_base_revc_2xaem/v8a/smp/ns (ARMv8-A SMP non-secure) The structure replaces the existing overly verbose board with a cleaner, more maintainable organization and provides a foundation for adding v9a variants. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add deprecated.cmake mappings to redirect old board names to new unified structure: - fvp_base_revc_2xaemv8a → fvp_base_revc_2xaem/v8a - fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp → fvp_base_revc_2xaem/v8a/smp - fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns → fvp_base_revc_2xaem/v8a/smp/ns This ensures existing build commands and documentation continue to work with deprecation warnings while transitioning to the new board structure. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add ARMv9-A architecture support with Cortex-A510 CPU as the default processor for generic ARMv9-A targets. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

New board targets: - fvp_base_revc_2xaem/v9a (basic ARMv9-A single core) - fvp_base_revc_2xaem/v9a/smp (ARMv9-A SMP 4 cores) - fvp_base_revc_2xaem/v9a/smp/ns (ARMv9-A SMP non-secure with TFA) Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add Cortex-A320 support to the unified FVP board structure with ARMv9.2-A specific configuration parameters. New board target: - fvp_base_revc_2xaem/a320 Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add comprehensive test to validate ARM64 architectural feature detection across ARMv8.1 through ARMv9-A implementations, providing runtime verification of processor capabilities and security features. Core architecture features tested: - Exception Level (EL) support detection (EL0-EL3) - SVE (Scalable Vector Extension) presence and capabilities - Advanced SIMD (NEON) and Floating Point implementation levels - Architecture version classification (ARMv8 vs ARMv9-A) ARMv8.1-A+ features: - LSE (Large System Extensions) atomic operations with level detection - Pointer Authentication (PAC) with comprehensive variant analysis: * API/APA (Address), GPI/GPA (Generic) authentication * Enhanced PAC levels (1, 3, 4, 5) with FPACCOMBINE detection * QARMA3 algorithm support (GPA3/APA3) ARMv8.5-A+ security and performance features: - Branch Target Identification (BTI) for control flow integrity - Memory Tagging Extensions (MTE) with level classification - Random Number Generation (RNDR) hardware entropy - Speculative Store Bypass Safe (SSBS) side-channel mitigation ARMv8.7-A+ advanced features: - WFxT (Wait with Timeout) enhanced synchronization - RPRES (Reciprocal Precision) optimized math operations ARMv8.8-A+ features: - MOPS (Memory Copy/Set) optimized memory operations - BC (Branch Consistency) advanced branch handling Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Implement Scalable Vector Extension (SVE) context switching support, enabling threads to use SVE instructions with lazy context preservation across task switches. The implementation is incremental: if only FPU instructions are used then only the NEON access is granted and preserved to minimize context switching overhead. If SVE is used then the NEON context is upgraded to SVE and then full SVE access is granted and preserved from that point onwards. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Add test to validate SVE (Scalable Vector Extension) context switching implementation, ensuring proper register preservation across thread switches in multi-threaded environments. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

Expand the SVE context switching test to cover all thread privilege combinations with validation of SVE state preservation across different contexts. Test Coverage: - Privileged vs Privileged threads (kernel mode) - User vs User threads (userspace with memory domains) - User vs Privileged threads (mixed privilege levels) Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

This fixes the following: CMakeStyle File:cmake/gcc-m-cpu.cmake Line:7 Column:Remove space before '(' in if() statements CMakeStyle File:cmake/gcc-m-cpu.cmake Line:22 Column:Remove space before '(' in if() statements CMakeStyle File:cmake/gcc-m-cpu.cmake Line:28 Column:Remove space before '(' in if() statements CMakeStyle File:cmake/gcc-m-cpu.cmake Line:38 Column:Remove space before '(' in if() statements CMakeStyle File:cmake/gcc-m-cpu.cmake Line:48 Column:Remove space before '(' in if() statements Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

sonarqubecloud · 2025-10-06T04:45:12Z

Quality Gate passed

Issues
7 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
1.3% Duplication on New Code

See analysis details on SonarQube Cloud

zephyrbot requested review from 57300, bjorniuppsala, dcpleung, gdengi, ithinuel, jeremybettis, JiafeiPan, LoveKarlsson, nashif, nordicjm, povergoing, RobinKastberg, SgrrZhf, tejlmand and wearyzen October 1, 2025 11:37

zephyrbot assigned nashif Oct 1, 2025

npitre force-pushed the armv9 branch 2 times, most recently from e17a152 to 4c67c12 Compare October 1, 2025 13:18

zephyrbot requested review from cfriedt, jhedberg, jukkar, kartben, rlubos and rodrigopex October 1, 2025 13:19

npitre force-pushed the armv9 branch 2 times, most recently from 79a135e to 1570dec Compare October 2, 2025 07:45

nordicjm requested changes Oct 2, 2025

View reviewed changes

npitre force-pushed the armv9 branch from 1570dec to 4c1423c Compare October 2, 2025 12:30

zephyrbot requested a review from nordicjm October 2, 2025 12:32

zephyrbot requested review from lorc, maass-hamburg and michalsimek October 3, 2025 11:39

npitre force-pushed the armv9 branch 3 times, most recently from cb177ff to 050a643 Compare October 3, 2025 12:59

nashif assigned wearyzen and unassigned nashif Oct 3, 2025

npitre force-pushed the armv9 branch from 050a643 to 72699b8 Compare October 3, 2025 13:14

npitre force-pushed the armv9 branch 3 times, most recently from 7e162a1 to 5df7a66 Compare October 6, 2025 04:01

Nicolas Pitre added 14 commits October 6, 2025 00:09

boards: arm: fvp_base_revc_2xaemv8a: allow SMP on bare metal

46d1d57

This adds necessary configuration files to build with SMP and no trusted firmware. Given PSCI is not available, CPU power management uses the FVP power controller directly. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

soc: arm: fvp_aem: Create unified SOC series structure

2e98d31

Reorganize fvp_aemv8a SOC into unified fvp_aem series with a v8a architecture variants to enable cleaner board target naming. This also sets the stage for upcoming ARMv9-A support. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

arch: arm64: Add ARMv9-A architecture and Cortex-A510 CPU support

8cf980a

Add ARMv9-A architecture support with Cortex-A510 CPU as the default processor for generic ARMv9-A targets. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

boards: arm: fvp: Add Cortex-A320 board variant support

c4ca233

Add Cortex-A320 support to the unified FVP board structure with ARMv9.2-A specific configuration parameters. New board target: - fvp_base_revc_2xaem/a320 Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

tests: arm64: Add SVE context switching validation test

b7ef204

Add test to validate SVE (Scalable Vector Extension) context switching implementation, ensuring proper register preservation across thread switches in multi-threaded environments. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>

npitre force-pushed the armv9 branch from 5df7a66 to dccba63 Compare October 6, 2025 04:25

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

ARM64 FVP Board Unification and ARMv9-A Support #96852

ARM64 FVP Board Unification and ARMv9-A Support #96852

npitre commented Oct 1, 2025 •

edited

Loading

Uh oh!

nordicjm Oct 2, 2025

Uh oh!

nordicjm Oct 2, 2025

Uh oh!

nordicjm Oct 2, 2025

Uh oh!

nordicjm Oct 2, 2025

Uh oh!

nordicjm Oct 2, 2025

Uh oh!

nordicjm Oct 2, 2025

Uh oh!

nordicjm Oct 2, 2025

Uh oh!

nordicjm Oct 2, 2025

Uh oh!

nordicjm Oct 2, 2025

Uh oh!

wearyzen commented Oct 2, 2025

Uh oh!

nashif commented Oct 3, 2025

Uh oh!

npitre commented Oct 3, 2025 via email

Uh oh!

sonarqubecloud bot commented Oct 6, 2025

Uh oh!

Uh oh!

	This board configuration supports multiple architecture variants:
	The following board targets are available:


		Cortex-A320 Configuration:

		The ``a320`` variant provides Cortex-A320 specific FVP configuration with:

ARM64 FVP Board Unification and ARMv9-A Support #96852

Are you sure you want to change the base?

ARM64 FVP Board Unification and ARMv9-A Support #96852

Conversation

npitre commented Oct 1, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

Choose a reason for hiding this comment

Uh oh!

wearyzen commented Oct 2, 2025

Uh oh!

nashif commented Oct 3, 2025

Uh oh!

npitre commented Oct 3, 2025 via email

Uh oh!

sonarqubecloud bot commented Oct 6, 2025

Quality Gate passed

Uh oh!

Uh oh!

npitre commented Oct 1, 2025 •

edited

Loading