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  • TKM College of Engineering
  • Kollam Kerala
  • 06:43 (UTC +05:30)

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CaptModTerm13/README.md

Electronics and Communication Engineering undergraduate with a keen interest in VLSI design and Embedded Systems. Passionate about exploring analog and digital VLSI domains using open-source EDA tools such as Xschem, NGSPICE, and Magic. Experienced in projects involving RISC-V processor design, ASIC design flow, microcontroller programming with ESP32 and ADI MAX78000FTHR, and Assembly and bare-metal programming using the 8051 microcontroller. Eager to contribute to cutting-edge VLSI research and semiconductor development.

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  1. Digital-Signal-Processing-Laboratory Digital-Signal-Processing-Laboratory Public

    MATLAB-based Digital Signal Processing Laboratory with examples of convolution, DFT, FIR filtering, and more. Each folder includes code and individual README files for theoretical explanations.

    MATLAB 1

  2. Current-Starved-VRO Current-Starved-VRO Public

  3. tt10-verilog-vlsi tt10-verilog-vlsi Public template

    Forked from TinyTapeout/tt10-verilog-template

    Submission template for Tiny Tapeout 10 - Verilog HDL Projects

    Verilog

  4. RISCV_SingleCycle RISCV_SingleCycle Public

    RISC V single cycle processor design and implementation using Bluespec System Verilog

    Bluespec 2 1