- Create the .bsv file (using a text editor)
- Compile the file using the command bsc -u file.bsv
- Perform .ba elaboration using the command bsc -u -sim -elab -g
- Perform .bo elaboration bsc -sim -e -o <TopName(Enter the alias for the sim file)>
- ./(filename) for simulation
-
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RISC V single cycle processor design and implementation using Bluespec System Verilog
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