[LoadOpToBlockIOConversion] Refactor block load codegen for regular pointer

[whitneywhtsang]

Refactors the 2D block load lowering to simplify regular pointer load code generation.
The codegen now relies on linear layout and getBlockIOTileSize.

PVC: https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/18207021859 (GOOD)
BMG: https://github.com/intel/intel-xpu-backend-for-triton/actions/runs/18207010226 (GOOD)

[Copilot]

Pull Request Overview

Refactors the 2D block load lowering to remove extensive DPAS-specific logic and simplify regular pointer load code generation. Key changes streamline mask constancy handling, compute load vector types directly, and introduce a new packing/unpacking path.

• Removes the multi-step DPAS operand decomposition logic and associated comments.
• Introduces a simplified computation of per-load element counts and restructuring of unpack/unpack insertion logic.
• Updates tests to reflect new block IO tiling behavior (tile_height/v_blocks adjustments and mask index expectations).

Reviewed Changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 4 comments.

File	Description
third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp	Refactors 2D block load lowering: removes DPAS-specific tiling/packing logic, adds new per-load computation and unpack path, adjusts mask/vBlocks handling.
test/TritonIntelGPU/tensor-pointer-load-block-2d.mlir	Updates CHECK patterns to match new tile shape, v_blocks, and constant/mask emission ordering.

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